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    Semiconductor integrated circuit device
    21.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08222945B2

    公开(公告)日：2012-07-17

    申请号：US13253584

    申请日：2011-10-05

    申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

    发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0016 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

    摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    22.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    半导体集成电路设备

    公开(公告)号：US20110068826A1

    公开(公告)日：2011-03-24

    申请号：US12957462

    申请日：2010-12-01

    申请人： Yuri AZUMA ,  Yoshihiko Yasu ,  Yasuto Igarashi ,  Takashi Kuraishi ,  Kazumasa Yanagisawa

    发明人： Yuri AZUMA ,  Yoshihiko Yasu ,  Yasuto Igarashi ,  Takashi Kuraishi ,  Kazumasa Yanagisawa

    IPC分类号： H03K19/0175

    CPC分类号： G11C5/147

    摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.

    摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。

    Semiconductor integrated circuit device
    24.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20060291110A1

    公开(公告)日：2006-12-28

    申请号：US11447168

    申请日：2006-06-06

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

    IPC分类号： H02H7/00

    CPC分类号： H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device is provided, the circuit being capable of arranging a control signal system, avoiding a danger of failure to check an indefinite signal propagation prevention circuit or the like, further facilitating a check oriented to mounting on an automated tool, and facilitating power shutdown control inside of a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains Area A to Area I. A rule is provided, the rule defining that, in the case where a circuit having a high priority is turned ON, a power domain having its lower priority cannot be turned OFF, thereby facilitating a designing method. In addition, areas capable of applying still another power supply are provided in the independent power areas Area A to Area I. In that area, a relay buffer (repeater) and a clock buffer or an information retaining latch for saving information are integrated. A layout may be provided in a direction vertical to a direction in which cells are arranged in a row direction for the purpose of dispersing a current of a light supply line.

    摘要翻译： 提供了一种半导体集成电路器件，该电路能够布置控制信号系统，避免不能检查不确定的信号传播防止电路等的危险，进一步便于针对安装在自动化工具上的检查，并且促进 功率关断控制芯片内部。 在半导体集成电路装置中，功率关闭优先级由独立的电源区域A至区域I提供。规定了在具有高优先级的电路被接通的情况下，规定了具有 其较低优先级不能关闭，从而有助于设计方法。 此外，在独立电源区域A至区域I中提供能够应用另一电源的区域。在该区域中，集成了用于保存信息的中继缓冲器（中继器）和时钟缓冲器或信息保持锁存器。 为了分散供电线的电流，布置可以沿垂直于单元布置在行方向上的方向设置。

    Semiconductor memory device
    25.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5818771A

    公开(公告)日：1998-10-06

    申请号：US723367

    申请日：1996-09-30

    申请人： Yoshihiko Yasu ,  Hiroyuki Sakai ,  Michael W. Yeager ,  Donald J. Verhaeghe

    发明人： Yoshihiko Yasu ,  Hiroyuki Sakai ,  Michael W. Yeager ,  Donald J. Verhaeghe

    IPC分类号： G11C16/02 ,  G06F12/14 ,  G06F21/02 ,  G11C7/24 ,  G11C11/22 ,  G11C7/00

    CPC分类号： G11C7/24 ,  G11C11/22

    摘要： A semiconductor memory device, divided into plural blocks, includes a memory array having a non-volatile memory element in which address access times for the read cycle and the write cycle are substantially equivalent to one another (for example, a ferroelectric memory element). Plural storage elements stores the information for write protection/permission corresponding to each of the blocks, respectively. A setting circuit is provided to set the information for write protection/permission to the plural storage elements. The setting circuit sets the write-protection information to the plural storage elements at the write cycle after designated plural read cycles. Therefore, the write protection/permission can be set in block units block by block, so that the write-protected areas for a ROM and a RAM formed by the non-volatile memory element can be set freely. Furthermore, the complexity of the setting procedure for write protection/permission serves to prevent accidental false setting caused by system runaway or the like.

    摘要翻译： 分为多个块的半导体存储器件包括具有非易失性存储元件的存储器阵列，其中读周期和写周期的地址访问时间彼此基本相等（例如，铁电存储元件）。 多个存储元件分别存储与每个块对应的写保护/许可的信息。 提供设置电路以将用于写入保护/许可的信息设置到多个存储元件。 设定电路在指定的多个读取周期之后以写入周期将写入保护信息设置为多个存储元件。 因此，可以逐块地以块为单位设置写入保护/许可，从而可以自由地设置由非易失性存储元件形成的ROM和RAM的写保护区域。 此外，写入保护/许可的设置过程的复杂性用于防止由系统失控等导致的意外错误设置。

    Semiconductor integrated circuit device
    29.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20070210404A1

    公开(公告)日：2007-09-13

    申请号：US11652013

    申请日：2007-01-11

    申请人： Satoshi Umekita ,  Tomomi Ajioka ,  Kenji Hirose ,  Yoshihiko Yasu ,  Yujiro Miyairi

    发明人： Satoshi Umekita ,  Tomomi Ajioka ,  Kenji Hirose ,  Yoshihiko Yasu ,  Yujiro Miyairi

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0203

    摘要： Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.

    摘要翻译： 中继器被布置在任意位置以显着提高信号的传输速度。 在半导体集成电路装置1中，在核心电源区域2,3和5的核心电源区域4的左侧设置有作为布线用继电器点的中继器的中继器区域10， 半导体集成电路装置1的上部和下部。中继器11的电源开关区域形成为围绕核心电源区域2至8和中继器区域10.参考电源线 连接到中继器区域10的电位在整个核心电源区域2至8中以均匀间隔布置，这使得中继器区域10能够被灵活布置。 这允许更有效地布置中继器，这改善了半导体集成电路装置1的性能。

    Semiconductor integrated circuit device
    30.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050218959A1

    公开(公告)日：2005-10-06

    申请号：US11048909

    申请日：2005-02-03

    申请人： Kentaro Yamawaki ,  Yoshihiko Yasu ,  Yasuto Igarashi ,  Takashi Kuraishi ,  Kazumasa Yanagisawa

    发明人： Kentaro Yamawaki ,  Yoshihiko Yasu ,  Yasuto Igarashi ,  Takashi Kuraishi ,  Kazumasa Yanagisawa

    IPC分类号： H01L21/822 ,  G06F1/00 ,  H01L23/522 ,  H01L27/02 ,  H01L27/04 ,  H03K17/687 ,  H03K19/00

    CPC分类号： H01L27/0207 ,  H01L23/5223 ,  H01L24/06 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3011 ,  H03K17/6871 ,  H03K19/0016 ,  H01L2924/00014 ,  H01L2924/00

    摘要： The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by: a first cell in which a first switch element for connecting a power supply voltage line or an ground voltage supply line to a power supply line of an internal circuit is disposed below a first pair of power supply lines extending in a first direction; a second cell in which a second switch element and a third switch element are disposed below a pair of second power supply lines extending in a second direction, the second switch element for connecting a first bias line connected to a first well region and a first back bias line, and the third switch element for connecting a second bias line connected to a second well region and a second back bias line; and a third cell in which a plurality of kinds of elements are spread, including a power supply switch controller for controlling the first switch element below a corner power supply line for connecting the first and pair of second power supply lines, fourth and fifth switch elements for connecting the corresponding power supply voltage line and the ground voltage supply line of the circuit to the first and second bias lines, and a control circuit for controlling switch between the fourth and fifth switch elements and the second and third switch elements.

    摘要翻译： 本发明提供一种提高设计效率同时实现更高功能的半导体集成电路器件。 内部电路包围：第一单元，其中用于将电源电压线或地电压线连接到内部电路的电源线的第一开关元件设置在第一对延伸的电源线的下方 第一个方向 第二单元，其中第二开关元件和第三开关元件设置在沿第二方向延伸的一对第二电源线的下方，所述第二开关元件用于连接连接到第一阱区的第一偏置线和第一背面 偏置线和用于连接连接到第二阱区和第二背偏置线的第二偏置线的第三开关元件; 以及第三单元，其中扩展了多种元件，包括用于将第一开关元件控制在用于连接第一和第二对第二电源线的角电源线下方的第一开关元件的第四开关元件和第五开关元件 用于将相应的电源电压线和电路的接地电压线连接到第一和第二偏置线;以及控制电路，用于控制第四和第五开关元件与第二和第三开关元件之间的开关。