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公开(公告)号：US20050218959A1
公开(公告)日：2005-10-06
申请号：US11048909
申请日：2005-02-03
IPC分类号： H01L21/822 , G06F1/00 , H01L23/522 , H01L27/02 , H01L27/04 , H03K17/687 , H03K19/00
CPC分类号： H01L27/0207 , H01L23/5223 , H01L24/06 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H03K17/6871 , H03K19/0016 , H01L2924/00014 , H01L2924/00
摘要： The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by: a first cell in which a first switch element for connecting a power supply voltage line or an ground voltage supply line to a power supply line of an internal circuit is disposed below a first pair of power supply lines extending in a first direction; a second cell in which a second switch element and a third switch element are disposed below a pair of second power supply lines extending in a second direction, the second switch element for connecting a first bias line connected to a first well region and a first back bias line, and the third switch element for connecting a second bias line connected to a second well region and a second back bias line; and a third cell in which a plurality of kinds of elements are spread, including a power supply switch controller for controlling the first switch element below a corner power supply line for connecting the first and pair of second power supply lines, fourth and fifth switch elements for connecting the corresponding power supply voltage line and the ground voltage supply line of the circuit to the first and second bias lines, and a control circuit for controlling switch between the fourth and fifth switch elements and the second and third switch elements.
摘要翻译： 本发明提供一种提高设计效率同时实现更高功能的半导体集成电路器件。 内部电路包围：第一单元，其中用于将电源电压线或地电压线连接到内部电路的电源线的第一开关元件设置在第一对延伸的电源线的下方 第一个方向 第二单元，其中第二开关元件和第三开关元件设置在沿第二方向延伸的一对第二电源线的下方，所述第二开关元件用于连接连接到第一阱区的第一偏置线和第一背面 偏置线和用于连接连接到第二阱区和第二背偏置线的第二偏置线的第三开关元件; 以及第三单元，其中扩展了多种元件，包括用于将第一开关元件控制在用于连接第一和第二对第二电源线的角电源线下方的第一开关元件的第四开关元件和第五开关元件 用于将相应的电源电压线和电路的接地电压线连接到第一和第二偏置线;以及控制电路，用于控制第四和第五开关元件与第二和第三开关元件之间的开关。
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公开(公告)号：US07411267B2
公开(公告)日：2008-08-12
申请号：US11048909
申请日：2005-02-03
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , H01L23/5223 , H01L24/06 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H03K17/6871 , H03K19/0016 , H01L2924/00014 , H01L2924/00
摘要： The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by a plurality of cells in which a first switch element for connecting a power supply voltage line or a ground voltage supply line to a power supply line of an internal circuit is disposed below power supply lines extending in a first and second directions, and the power lines are connected together.
摘要翻译： 本发明提供一种提高设计效率同时实现更高功能的半导体集成电路器件。 内部电路被多个单元包围，其中用于将电源电压线或接地电压供给线连接到内部电路的电源线的第一开关元件设置在第一和第二电极中延伸的电源线之下 方向，电源线连接在一起。
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公开(公告)号：US20110068826A1
公开(公告)日：2011-03-24
申请号：US12957462
申请日：2010-12-01
IPC分类号： H03K19/0175
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.
摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。
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公开(公告)号：US20050232053A1
公开(公告)日：2005-10-20
申请号：US11109660
申请日：2005-04-20
IPC分类号： H01L21/822 , G11C5/00 , G11C5/14 , H01L27/04 , H03K19/00 , H03K19/0175
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has a first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed, wherein the second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with the control signal which was responded to when the second power supply state was instructed by the third circuit block to the first circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block.
摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路器件具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块的指令或第二电源确保第一电路块中的内部电路的操作 其中第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有根据本发明的输入电路，其中内部电路的操作不被保证， 当第三电路块向第一电路块指示第二电源状态时响应的控制信号使得将特定信号电平维持为与第二电路块的工作电压无关，而与信号无关 由第一电路块提供。
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公开(公告)号：US07855593B2
公开(公告)日：2010-12-21
申请号：US12497982
申请日：2009-07-06
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.
摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。
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公开(公告)号：US20090267686A1
公开(公告)日：2009-10-29
申请号：US12497982
申请日：2009-07-06
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.
摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。
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7.发明授权Semiconductor integrated circuit device having an improved operation control for a dynamic memory 失效具有用于动态存储器的改进的操作控制的半导体集成电路器件公开(公告)号：US06301184B1
公开(公告)日：2001-10-09
申请号：US09480695
申请日：2000-01-11
申请人： Toshio Sasaki , Yoshihiko Yasu , Kazumasa Yanagisawa , Yuji Tanaka , Toshiaki Takahira , Yasuto Igarashi , Mariko Ohtsuka , Yasunobu Aoki
发明人： Toshio Sasaki , Yoshihiko Yasu , Kazumasa Yanagisawa , Yuji Tanaka , Toshiaki Takahira , Yasuto Igarashi , Mariko Ohtsuka , Yasunobu Aoki
IPC分类号： G11C800
CPC分类号： G11C11/4074 , G11C7/1045
摘要： A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.
摘要翻译： 将DRAM模块应用于具有用于抑制其整体操作的待机模式的系统LSI和至少允许DRAM模块操作但抑制其它电路的操作的操作待机模式。 将上述模式以及衬底偏置控制技术应用于在低电压下工作的CMOS系统LSI。 控制系统LSI以保持或不保存数据，使得能够安装大容量的存储器并消耗足够的电力量。
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公开(公告)号：US20100219800A1
公开(公告)日：2010-09-02
申请号：US12714309
申请日：2010-02-26
申请人： Kazuki FUKUOKA , Yasuto Igarashi , Ryo Mori , Yoshihiko Yasu , Toshio Sasaki
发明人： Kazuki FUKUOKA , Yasuto Igarashi , Ryo Mori , Yoshihiko Yasu , Toshio Sasaki
IPC分类号： G05F1/10
CPC分类号： H03K5/00 , H01L27/0203 , H01L27/0207 , H01L27/0928 , H01L27/11807 , H03K3/00 , H03K19/0016
摘要： Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.
摘要翻译： 通过使用电源开关控制和DVFS技术组合实现断电电路技术实现功耗的有效降低，实现低功耗。 在半导体基板上形成的DEEP-NWELL区域中，形成供给电源电压的电源开关部，由电源开关部进行电源切断的电路块和电平移位器。 供给另一电源电压的另一个电源开关部分，由电源开关部分执行电源切断的电路块和电平移位器形成在形成在半导体衬底上的另一个DEEP-NWELL区域中。 在这种布置中，不存在通过半导体衬底上形成的每个DEEP-NWELL区域在不同电源之间短路的可能性。
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公开(公告)号：US08379425B2
公开(公告)日：2013-02-19
申请号：US12714309
申请日：2010-02-26
申请人： Kazuki Fukuoka , Yasuto Igarashi , Ryo Mori , Yoshihiko Yasu , Toshio Sasaki
发明人： Kazuki Fukuoka , Yasuto Igarashi , Ryo Mori , Yoshihiko Yasu , Toshio Sasaki
CPC分类号： H03K5/00 , H01L27/0203 , H01L27/0207 , H01L27/0928 , H01L27/11807 , H03K3/00 , H03K19/0016
摘要： Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.
摘要翻译： 通过使用电源开关控制和DVFS技术组合实现断电电路技术实现功耗的有效降低，实现低功耗。 在半导体基板上形成的DEEP-NWELL区域中，形成供给电源电压的电源开关部，由电源开关部进行电源切断的电路块和电平移位器。 供给另一电源电压的另一个电源开关部分，由电源开关部分执行电源切断的电路块和电平移位器形成在形成在半导体衬底上的另一个DEEP-NWELL区域中。 在这种布置中，不存在通过半导体衬底上形成的每个DEEP-NWELL区域在不同电源之间短路的可能性。
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公开(公告)号：US08242541B2
公开(公告)日：2012-08-14
申请号：US11651076
申请日：2007-01-09
申请人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
发明人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
IPC分类号： H01L27/118
CPC分类号： H04B3/32
摘要： A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.
摘要翻译： 减少半导体装置中的串扰噪声等外部噪声的影响的技术，以防止电路发生故障。 易受噪声影响的真实信号线和条形信号线，以及电平移位器电路的输入信号线的一部分以及用于屏蔽这些信号线的屏蔽线布置在I / O单元上。 这样的I / O单元被并排放置以完成真正的信号线连接和条形信号线连接。 这些导线布置成通过多个I / O单元并且彼此平行或多层。
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