公开(公告)号：US08872227B2

公开(公告)日：2014-10-28

申请号：US13402631

申请日：2012-02-22

Applicant: Hidekazu Umeda ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Hidekazu Umeda ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/2003 ,  H01L29/1066 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

Abstract: A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

Abstract translation: 氮化物半导体器件包括半导体衬底和形成在半导体衬底上的氮化物半导体层。 半导体衬底包括正常区域和围绕法线区域的界面电流阻挡区域。 氮化物半导体层包括元件区域和围绕元件区域的隔离区域。 元件区域形成在正常区域上。 界面电流阻挡区域含有杂质，并且在氮化物半导体层和半导体衬底之间的界面处产生的载流子形成势垒。

公开(公告)号：US08779438B2

公开(公告)日：2014-07-15

申请号：US13569014

申请日：2012-08-07

Applicant: Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

Inventor： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract translation: 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US08742467B2

公开(公告)日：2014-06-03

申请号：US13613724

申请日：2012-09-13

Applicant: Tatsuo Morita ,  Daisuke Ueda ,  Yasuhiro Uemoto ,  Tetsuzo Ueda

Inventor： Tatsuo Morita ,  Daisuke Ueda ,  Yasuhiro Uemoto ,  Tetsuzo Ueda

IPC: H01L29/772 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003

Abstract: A bidirectional switching device includes a semiconductor multilayer structure made of a nitride semiconductor, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor multilayer structure, and a first gate electrode and a second gate electrode. The first gate electrode is covered with a first shield electrode having a potential substantially equal to that of the first ohmic electrode. The second gate electrode is covered with the second shield electrode having a potential substantially equal to that of the second ohmic electrode. An end of the first shield electrode is positioned between the first gate electrode and the second gate electrode, and an end of the second shield electrode is positioned between the second gate electrode and the first gate electrode.

Abstract translation: 双向开关器件包括由半导体多层结构上形成的由氮化物半导体，第一欧姆电极和第二欧姆电极构成的半导体多层结构以及第一栅电极和第二栅电极。 第一栅电极被第一屏蔽电极覆盖，该第一屏蔽电极的电位基本上等于第一欧姆电极的电位。 第二栅电极被第二屏蔽电极覆盖，其电位基本上等于第二欧姆电极的电位。 第一屏蔽电极的端部位于第一栅极电极和第二栅极电极之间，第二屏蔽电极的端部位于第二栅极电极和第一栅极电极之间。

公开(公告)号：US08569797B2

公开(公告)日：2013-10-29

申请号：US13185818

申请日：2011-07-19

Applicant: Hidekazu Umeda ,  Masahiro Hikita ,  Tetsuzo Ueda

Inventor： Hidekazu Umeda ,  Masahiro Hikita ,  Tetsuzo Ueda

IPC: H01L29/80

CPC classification number: H01L29/7783 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.

Abstract translation: 场效应晶体管包括形成在衬底上的第一半导体层和第二半导体层。 第一半导体层具有设置为包含非导电杂质的隔离区域的含有区域和不含非导电杂质的非含有区域。 第一区域由容纳区域和非含有区域之间的界面的一部分的附近限定，界面的部分在栅电极下方，包括界面部分的附近包含在包含 地区。 第二半导体层包括位于第一区域正上方的第二区域。 第二区域的非导电性杂质的浓度低于第一区域的浓度。

公开(公告)号：US08344423B2

公开(公告)日：2013-01-01

申请号：US13360275

申请日：2012-01-27

Applicant: Yasuhiro Uemoto ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Yasuhiro Uemoto ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7783

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

Abstract translation: 氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。 位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域 形成有具有比控制区域更高的电阻的高电阻区域。

公开(公告)号：US20120299011A1

公开(公告)日：2012-11-29

申请号：US13569014

申请日：2012-08-07

Applicant: Masahiro HIKITA ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

Inventor： Masahiro HIKITA ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC: H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract translation: 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US20120119261A1

公开(公告)日：2012-05-17

申请号：US13356156

申请日：2012-01-23

Applicant: Hidekazu UMEDA ,  Tetsuzo Ueda

Inventor： Hidekazu UMEDA ,  Tetsuzo Ueda

IPC: H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462

Abstract: A semiconductor device includes: a substrate 101, a first nitride semiconductor layer 104S which includes a plurality of nitride semiconductor layers formed on the substrate 101, and has a channel region; a second semiconductor layer 105 which is formed on the first nitride semiconductor layer 104S, and has a conductivity type opposite a conductivity type of the channel region; a conductive layer which is in contact with the second semiconductor layer 105, and includes a metal layer 107 or a high carrier concentration semiconductor layer having a carrier concentration of 1×1018 cm−3 or higher; an insulating layer 110 formed on the conductive layer; a gate electrode 111 formed on the insulating layer 110; and a source electrode 108 and a drain electrode 109 formed to laterally sandwich the second semiconductor layer 105.

Abstract translation: 半导体器件包括：衬底101，包括形成在衬底101上的多个氮化物半导体层的第一氮化物半导体层104S，并具有沟道区; 第二半导体层105，其形成在第一氮化物半导体层104S上，并且具有与沟道区的导电类型相反的导电类型; 与第二半导体层105接触的导体层，具有载流子浓度为1×1018 cm -3以上的金属层107或高载流子浓度半导体层; 形成在导电层上的绝缘层110; 形成在绝缘层110上的栅电极111; 以及形成为横向夹持第二半导体层105的源电极108和漏电极109。

公开(公告)号：US20110175142A1

公开(公告)日：2011-07-21

申请号：US13120382

申请日：2009-08-26

Applicant: Naohiro Tsurumi ,  Satoshi Nakazawa ,  Tetsuzo Ueda

Inventor： Naohiro Tsurumi ,  Satoshi Nakazawa ,  Tetsuzo Ueda

IPC: H01L29/80

CPC classification number: H01L29/1075 ,  H01L23/481 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nitride semiconductor device includes a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer, and having a wider bad gap than the first nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, which are formed on the second nitride semiconductor layer; a high resistive layer formed lower than the first nitride semiconductor layer; a conductive layer formed under and in contact with the high resistive layer; a lower insulating layer formed under the conductive layer; and a bias terminal electrically connected to the conductive layer.

Abstract translation: 氮化物半导体器件包括第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的不良间隙的第二氮化物半导体层; 源电极，漏电极和栅电极，形成在第二氮化物半导体层上; 形成为低于第一氮化物半导体层的高电阻层; 形成在所述高电阻层之下并与所述高电阻层接触的导电层; 形成在导电层下面的下绝缘层; 以及电连接到所述导电层的偏置端子。

公开(公告)号：US07956383B2

公开(公告)日：2011-06-07

申请号：US12060505

申请日：2008-04-01

Applicant: Masayuki Kuroda ,  Tetsuzo Ueda

Inventor： Masayuki Kuroda ,  Tetsuzo Ueda

IPC: H01L31/072

CPC classification number: H01L29/7787 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/518 ,  H01L29/66462

Abstract: A field effect transistor includes: a first nitride semiconductor layer having a plane perpendicular to a (0001) plane or a plane tilted with respect to the (0001) plane as a main surface; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; and a source electrode and a drain electrode formed so as to contact at least a part of the second nitride semiconductor layer or the third nitride semiconductor layer. A recess that exposes a part of the second nitride semiconductor layer is formed between the source electrode and the drain electrode in the third nitride semiconductor layer. A gate electrode is formed in the recess and an insulating film is formed between the third nitride semiconductor layer and the gate electrode.

Abstract translation: 场效应晶体管包括：具有垂直于（0001）面的平面或相对于（0001）面倾斜的平面作为主表面的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 形成在所述第二氮化物半导体层上的第三氮化物半导体层; 以及形成为与第二氮化物半导体层或第三氮化物半导体层的至少一部分接触的源电极和漏电极。 在第三氮化物半导体层中的源电极和漏电极之间形成露出第二氮化物半导体层的一部分的凹部。 在凹部中形成栅电极，在第三氮化物半导体层和栅电极之间形成绝缘膜。

公开(公告)号：US07873090B2

公开(公告)日：2011-01-18

申请号：US11519973

申请日：2006-09-13

Applicant: Toshikazu Onishi ,  Tetsuzo Ueda ,  Daisuke Ueda

Inventor： Toshikazu Onishi ,  Tetsuzo Ueda ,  Daisuke Ueda

IPC: H01S5/068 ,  H01S5/183 ,  H01S5/02 ,  H01S5/42

CPC classification number: H01S5/18355 ,  B82Y20/00 ,  H01L31/035281 ,  H01L31/105 ,  H01S5/02284 ,  H01S5/0425 ,  H01S5/18311 ,  H01S5/18319 ,  H01S5/18344 ,  H01S5/18358 ,  H01S5/18386 ,  H01S5/3432 ,  H01S5/423 ,  Y02E10/50

Abstract: A surface emitting laser includes a plurality of light-emitting portions for emitting laser light beams in different linearly polarized light directions. The light-emitting portions are formed on the substrate and located close to each other. The light-emitting portions include metal opening arrays through which light beams in different linearly polarized light directions respectively pass.

Abstract translation: 表面发射激光器包括用于在不同的线偏振光方向上发射激光束的多个发光部分。 发光部分形成在基板上并且彼此靠近。 发光部分包括分别通过不同线偏振光方向的光束的金属开口阵列。