公开(公告)号：US08455363B2

公开(公告)日：2013-06-04

申请号：US13282593

申请日：2011-10-27

Applicant: Tzung-Han Lee ,  Chung-Lin Huang

Inventor： Tzung-Han Lee ,  Chung-Lin Huang

IPC: H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/3083

Abstract: A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.

Abstract translation: 用于调整衬底的沟槽深度的方法具有以下步骤。 在衬底上形成图案化的覆盖层，其中图案化覆盖层限定更宽的间隔和更窄的间隔。 形成更宽的间隔布置的较宽的缓冲层和以较窄的间隔布置的较窄的缓冲层。 较窄的缓冲层的厚度比较宽的缓冲层薄。 实施干蚀刻工艺以使与较宽和较窄缓冲层相对应的衬底形成多个沟槽。 当蚀刻较宽和较窄的缓冲层时，首先去除较窄的缓冲层，使得对应于较窄缓冲层的衬底将比对应于较宽缓冲层的衬底早蚀刻。

公开(公告)号：US08298892B1

公开(公告)日：2012-10-30

申请号：US13241295

申请日：2011-09-23

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L21/76224 ,  H01L29/4236

Abstract: A fabricating method of an insulator for replacing a gate structure in a substrate by the insulator. The fabricating method includes the step of providing a substrate including a first buried gate structure. The first buried structure includes a first trench embedded in the substrate and a first gate filling in the first trench. The first trench has a first depth. Then, the first gate of the first buried structure is removed. Later, the substrate under the first trench is etched to elongate the depth of the first trench from the first depth to a third depth. Finally, an insulating material fills in the first trench with the third depth to form an insulator of the present invention.

Abstract translation: 一种绝缘体的制造方法，用于通过绝缘体代替衬底中的栅极结构。 制造方法包括提供包括第一掩埋栅极结构的衬底的步骤。 第一掩埋结构包括嵌入衬底中的第一沟槽和填充在第一沟槽中的第一栅极。 第一个沟槽有第一个深度。 然后，去除第一掩埋结构的第一栅极。 之后，蚀刻第一沟槽下面的衬底，以将第一沟槽的深度从第一深度延伸到第三深度。 最后，绝缘材料填充具有第三深度的第一沟槽以形成本发明的绝缘体。

公开(公告)号：US20120012907A1

公开(公告)日：2012-01-19

申请号：US12874232

申请日：2010-09-02

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC: H01L27/108

CPC classification number: H01L29/4983 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/4236

Abstract: A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

Abstract translation: 公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉 位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸 （边缘壁），以执行侧壁接触。 自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

公开(公告)号：US08557673B1

公开(公告)日：2013-10-15

申请号：US13476251

申请日：2012-05-21

Applicant: Shin-Bin Huang ,  Cheng-Yeh Hsu ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Cheng-Yeh Hsu ,  Chung-Lin Huang

IPC: H01L21/02

CPC classification number: H01L28/91

Abstract: A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers.

Abstract translation: 提供一种电容器结构的制造方法，其包括以下步骤：在具有第一氧化物层的衬底上，（a）在第一氧化物层上形成第一悬浮层; （b）在衬底上方的第一氧化物层中形成第一浅沟槽; （c）形成填充所述第一浅沟槽的第二氧化物层; （d）在第二氧化物层上形成第二悬浮层; （e）通过所述第二悬浮层形成穿过所述第一悬浮层上方的所述第二氧化物层的第二浅沟槽; （f）通过第二和第一氧化物层在第二浅沟槽的底表面上形成至少一个深沟槽，（g）在深沟槽的内表面上形成电极层; 和（h）通过第一和第二悬浮层中的沟槽开口去除第一和第二氧化物层。

公开(公告)号：US07868377B2

公开(公告)日：2011-01-11

申请号：US11927616

申请日：2007-10-29

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/94

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

Abstract translation: 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅晶体管的选通栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US07682902B2

公开(公告)日：2010-03-23

申请号：US11949786

申请日：2007-12-04

Applicant: Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

Inventor： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

IPC: H01L21/336

CPC classification number: H01L27/11534 ,  H01L21/84 ,  H01L27/11526 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

Abstract: A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

Abstract translation: 本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。 一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。 然后，在第一凹槽上形成第一栅极电介质层。 第一导电层形成在第一栅极介电层上。 之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。 在第一凹槽的底部形成第二凹槽。 在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。 形成为填充第一和第二凹槽的第二导电层。

公开(公告)号：US06921694B2

公开(公告)日：2005-07-26

申请号：US10442308

申请日：2003-05-19

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.

Abstract translation: 一种用于制造具有多个尖端的浮动栅极的方法。 提供半导体衬底，其上依次形成绝缘层和图案化的硬掩模层。 图案化的硬掩模层具有露出半导体衬底的表面的开口。 在图案化的硬掩模层上共形形成导电层，并且该开口填充有导电层。 导电层被平坦化以暴露图案化的硬掩模层的表面。 导电层被热氧化以形成氧化物层，去除图案化的硬掩模层。

公开(公告)号：US06768164B2

公开(公告)日：2004-07-27

申请号：US10725052

申请日：2003-12-01

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

公开(公告)号：US06451654B1

公开(公告)日：2002-09-17

申请号：US10029429

申请日：2001-12-18

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer are successively formed on a semiconductor substrate, and a first insulating spacer is formed on their sidewalls. Then, shallow trench isolation (STI) is formed in the substrate using the first patterned mask layer and the first insulating spacer as a mask. Then, the first patterned mask layer and a part of the first insulating spacer are removed to expose the first patterned polysilicon layer. A floating gate region is defined on the first patterned polysilicon layer, and the surface of the first polysilicon layer in the floating gate region is selectively oxidized to form polysilicon oxide layer. Then, the polysilicon oxide layer is used as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate. Finally, an intergate insulating layer and a second patterned polysilicon layer as a control gate are succesively formed on the polysilicon oxide layer. The present invention forms a floating gate in a self-aligned manner, which can decreases critical dimension. When an oxidation process is conducted to form the above polysilicon oxide layer, the nitride liner layer and the insulating spacer formed in the trench protect the sides of floating gate from oxygen invasion. This prevents the line width of floating gate from size reduction. Current leakage is also be avoided.

Abstract translation: 本发明提供一种用于制造自对准分离栅闪存的方法。 首先，在半导体衬底上依次形成图案化栅极氧化物层，第一图案化多晶硅层和第一图案化掩模层，并且在其侧壁上形成第一绝缘间隔物。 然后，使用第一图案化掩模层和第一绝缘间隔物作为掩模在衬底中形成浅沟槽隔离（STI）。 然后，去除第一图案化掩模层和第一绝缘间隔物的一部分以露出第一图案化多晶硅层。 在第一图案化多晶硅层上限定浮栅区域，并且浮栅区域中的第一多晶硅层的表面被选择性地氧化以形成多晶硅氧化物层。 然后，将多晶硅氧化物层用作掩模，以自对准的方式去除下面的第一多晶硅层以形成浮动栅极。 最后，在多晶硅氧化物层上连续地形成作为控制栅极的栅极绝缘层和第二图案化多晶硅层。 本发明以自对准的方式形成浮动栅极，这可以降低临界尺寸。 当进行氧化处理以形成上述多晶硅氧化物层时，形成在沟槽中的氮化物衬垫层和绝缘衬垫保护浮动栅极的侧面免受氧气侵入。 这样可以防止浮动栅极的线宽缩小。 电流泄漏也被避免。

公开(公告)号：US07981743B2

公开(公告)日：2011-07-19

申请号：US12039744

申请日：2008-02-29

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568

Abstract: The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.

Abstract translation: 本发明的存储单元具有分别嵌入控制门的两个相对的侧壁中的两个独立的存储区域。 以这种方式，数据存储可以更可靠。 本发明的其他特征是电介质层的厚度不同，并且两个独立的存储区域通过蚀刻工艺形成在开口的相对的底侧上并形成像间隔物的形状。 上述方法的优点是简化了制造工艺，并且减少了自对准的难度。