公开(公告)号：US09991266B2

公开(公告)日：2018-06-05

申请号：US15180095

申请日：2016-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen

IPC: H01L27/108 ,  H01L29/423 ,  H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L23/528

CPC classification number: H01L27/10814 ,  H01L23/528 ,  H01L27/10897 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/42356 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. The memory cells are arranged in an array and electrically connected to corresponding bit lines and word lines respectively, and any two memory cells adjacent to each other share a same oxide semiconductor layer as a channel layer. The present invention also relates to a semiconductor memory device including two memory cells sharing a same oxide semiconductor layer as a channel layer.

公开(公告)号：US20180138316A1

公开(公告)日：2018-05-17

申请号：US15853875

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Chen-Bin Lin ,  SANPO WANG ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

公开(公告)号：US09899365B1

公开(公告)日：2018-02-20

申请号：US15409498

申请日：2017-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/0207 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A layout of a semiconductor device includes a first active area, a second active area, plural gates, a first conductive layout and plural plugs. The first and the second active areas are disposed on a substrate and surrounded by a shallow trench isolation (STI). The plural gates are parallel with one another and cross the first and the second active areas. The first conductive layer covers the plural gates, and the plural gates are electrically connected to each other through the first conductive layer. The plural plugs are disposed on the first conductive layer to electrically connect the plural gates.

公开(公告)号：US09728454B1

公开(公告)日：2017-08-08

申请号：US15242611

申请日：2016-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L21/76895 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475

Abstract: The present invention provides a semiconductor structure, includes a substrate, a dielectric layer disposed on the substrate, a first gate structure and a second gate structure disposed in the dielectric layer, a hard mask disposed in the dielectric layer, where the hard mask covers a sidewall of the first gate structure, and covers the second gate structure, and a contact structure disposed in the dielectric layer. The contact structure at least crosses over the hard mask. The contact structure includes a first contact portion and a second contact portion. The first contact portion contacts the first gate structure directly, the second contact portion contacts the substrate directly, and the hard mask is disposed between the first contact portion and the second contact portion.

公开(公告)号：US20230178657A1

公开(公告)日：2023-06-08

申请号：US18103505

申请日：2023-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/51 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/1037

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

公开(公告)号：US11011649B2

公开(公告)日：2021-05-18

申请号：US16027386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L21/426 ,  H01L27/12 ,  H01L29/49

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US20210126131A1

公开(公告)日：2021-04-29

申请号：US17140114

申请日：2021-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

公开(公告)号：US10727234B2

公开(公告)日：2020-07-28

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  Runshun Wang ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

公开(公告)号：US20180331233A1

公开(公告)日：2018-11-15

申请号：US16027386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L21/426 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/426 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US09887293B2

公开(公告)日：2018-02-06

申请号：US15191542

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Chen-Bin Lin ,  Sanpo Wang ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.