公开(公告)号：US20200144102A1

公开(公告)日：2020-05-07

申请号：US16181354

申请日：2018-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Shi-You Liu ,  Shao-Hua Hsu

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3115

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.

公开(公告)号：US10340268B2

公开(公告)日：2019-07-02

申请号：US15284552

申请日：2016-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/51 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

公开(公告)号：US09966266B2

公开(公告)日：2018-05-08

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/02 ,  H01L21/268 ,  H01L21/67 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/687 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

公开(公告)号：US20170179286A1

公开(公告)日：2017-06-22

申请号：US14978409

申请日：2015-12-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02636 ,  H01L21/0332 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.

公开(公告)号：US09627534B1

公开(公告)日：2017-04-18

申请号：US14946795

申请日：2015-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/26 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L23/00 ,  H01L23/535 ,  H01L29/267 ,  H01L21/265

CPC classification number: H01L21/0335 ,  H01L21/02521 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/3105 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an ILD layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region.

公开(公告)号：US09613808B1

公开(公告)日：2017-04-04

申请号：US15001094

申请日：2016-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/32139

Abstract: A method of forming a multilayer hard mask includes the following steps. An unpatterned multilayer hard mask is formed on a semiconductor substrate. The unpatterned multilayer hard mask includes a first hard mask layer formed on the semiconductor substrate and a second hard mask layer directly formed on the first hard mask layer. A treatment is performed on a top surface of the first hard mask layer before the step of forming the second hard mask layer, and the treatment is configured to remove impurities on the first hard mask layer and form dangling bonds on the top surface of the first hard mask layer. Defects related to the first hard mask layer and the second hard mask layer may be reduced, and the manufacturing yield may be enhanced accordingly.