公开(公告)号：US10366991B1

公开(公告)日：2019-07-30

申请号：US15880492

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Yu-Ying Lin ,  Yen-Hsing Chen ,  Chun-Jen Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

公开(公告)号：US10199485B2

公开(公告)日：2019-02-05

申请号：US15409467

申请日：2017-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L29/08 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306

Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.

公开(公告)号：US20180204939A1

公开(公告)日：2018-07-19

申请号：US15409467

申请日：2017-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/775 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L29/775 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/125 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.

公开(公告)号：US20190280106A1

公开(公告)日：2019-09-12

申请号：US16404749

申请日：2019-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Yi-Liang Ye ,  Sung-Yuan Tsai ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Zhen Wu ,  Tai-Yen Lin

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/285 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

公开(公告)号：US10332981B1

公开(公告)日：2019-06-25

申请号：US15943657

申请日：2018-04-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Yi-Liang Ye ,  Sung-Yuan Tsai ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Zhen Wu ,  Tai-Yen Lin

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L21/285 ,  H01L21/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

公开(公告)号：US10128366B2

公开(公告)日：2018-11-13

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan Ku ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu Lin ,  Chun Yao Yang ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L29/417 ,  H01L29/165 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US20180158943A1

公开(公告)日：2018-06-07

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan KU ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu LIN ,  Chun Yao YANG ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/165 ,  H01L29/06 ,  H01L21/225 ,  H01L21/768 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/0922 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US09741572B1

公开(公告)日：2017-08-22

申请号：US15049152

申请日：2016-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Chun-Wei Yu ,  Yu-Ying Lin ,  Yu-Ren Wang

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L21/28167 ,  H01L21/823462 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.

公开(公告)号：US09502244B2

公开(公告)日：2016-11-22

申请号：US15166291

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuang-Hsiu Chen ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L21/76 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/265

CPC classification number: H01L21/02636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, next, a first dry etching process is performed, to form a recess in the substrate. Afterwards, an ion implantation process is performed to a bottom surface of the recess, a wet etching process is then performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively, and a second dry etching process is performed, to etch partial bottom surface of the recess, wherein after the second dry etching process is performed, a lower portion of the recess has a U-shaped cross section profile.

Abstract translation: 本发明提供一种形成半导体结构的方法，包括：首先提供衬底，然后进行第一干蚀刻工艺，以在衬底中形成凹陷。 之后，对凹部的底面执行离子注入工艺，然后执行湿蚀刻工艺，以蚀刻凹部的部分侧壁，从而分别在凹槽的两侧形成至少两个尖端，并且 进行第二干蚀刻工艺，以蚀刻凹部的部分底表面，其中在执行第二干蚀刻工艺之后，凹部的下部具有U形横截面轮廓。

公开(公告)号：US09966266B2

公开(公告)日：2018-05-08

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/02 ,  H01L21/268 ,  H01L21/67 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/687 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.