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    Semiconductor device including elongated bonding structure between the substrate
    22.
    发明授权
    Semiconductor device including elongated bonding structure between the substrate 有权

    公开(公告)号：US11569188B2

    公开(公告)日：2023-01-31

    申请号：US17387755

    申请日：2021-07-28

    Applicant: United Microelectronics Corp.

    Inventor： Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin

    IPC: H01L21/68 ,  H01L23/00

    Abstract: A semiconductor device, including a first semiconductor substrate and a second semiconductor substrate, is provided. A first bonding structure is located on the first semiconductor substrate and includes a first pad having an elongated shape. A second bonding structure is located on the second semiconductor substrate and includes a second pad having an elongated shape. The first semiconductor substrate is bonded to the second semiconductor substrate by bonding the first bonding structure and the second bonding structure. The first pad is bonded to the second pad, and an extension direction of the first pad is different from an extension direction of the second pad.

    SEMICONDUCTOR PACKAGE STRUCTURE
    23.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权

    公开(公告)号：US20210005559A1

    公开(公告)日：2021-01-07

    申请号：US17023967

    申请日：2020-09-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

    IPC: H01L23/64 ,  H01L23/31

    Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

    MANUFACTURING METHOD OF DIE-STACK STRUCTURE
    25.
    发明申请
    MANUFACTURING METHOD OF DIE-STACK STRUCTURE 审中-公开

    公开(公告)号：US20190259725A1

    公开(公告)日：2019-08-22

    申请号：US16402058

    申请日：2019-05-02

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Tse Lin

    IPC: H01L23/00 ,  H01L23/48 ,  H05K3/46 ,  H01L25/065

    Abstract: The present disclosure provides a manufacturing method of a die-stack structure including follow steps. A first wafer including a first die is provided, wherein the first die includes a first substrate material layer, a first interconnect structure, and a first pad, and the first interconnect structure and the first pad are formed on the first substrate material layer in order, and the first substrate material layer has a first contact conductor disposed therein. The first contact conductor is disposed in the first substrate material layer. A second wafer including a second die is provided, wherein the second die includes a second substrate material layer, a second interconnect structure, and a second pad, and the second interconnect structure and the second pad are formed on the second substrate material layer in order, and the second substrate material layer has a second contact conductor disposed therein. A portion of the first substrate material layer is removed to form a first substrate, wherein the first contact conductor is exposed to a surface of the first substrate away from the first interconnect structure. The second wafer is covered on the first substrate such that the first contact conductor is directly physically in contact with the second pad.

    Chip-stack structure
    26.
    发明授权
    Chip-stack structure 有权

    公开(公告)号：US10325873B2

    公开(公告)日：2019-06-18

    申请号：US15673223

    申请日：2017-08-09

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Tse Lin

    IPC: H01L25/04 ,  H01L25/07 ,  H01L25/11 ,  H01L23/00 ,  H01L25/065 ,  H05K3/46 ,  H01L25/075

    Abstract: A chip-stack structure including a first chip and a second chip located on the first chip is provided. The first chip includes a first substrate, a first interconnect structure, a first pad, and a first contact conductor. The first interconnect structure is located on a first surface of the first substrate. The first pad is located on the first interconnect structure. The first contact conductor is located in the first substrate and exposed on a second surface of the first substrate opposite to the first surface. The second chip includes a second substrate, a second interconnect structure, a second pad, and a second contact conductor. The second interconnect structure is located on the second substrate. The second pad is located on the second interconnect structure. The second contact conductor is located in the second substrate, wherein the first contact conductor is directly physically in contact with the second pad.

    Interposer structure and manufacturing method thereof
    29.
    发明授权
    Interposer structure and manufacturing method thereof 有权
    内插器结构及其制造方法

    公开(公告)号：US09412686B2

    公开(公告)日：2016-08-09

    申请号：US14468329

    申请日：2014-08-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chien-Li Kuo

    IPC: H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H01L21/311

    CPC classification number: H01L23/49811 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to an interposer structure and a manufacturing method thereof. The interposer structure includes a first dielectric layer, a conductive pad, and a bump. The conductive pad is disposed in the first dielectric layer, wherein a top surface of the conductive pad is exposed from a first surface of the first dielectric layer, the conductive pad further includes a plurality of connection feet, and the connection feet protrude from a bottom surface of the conductive pad to a second surface of the first dielectric layer. The bump is disposed on the second surface of the first dielectric layer, and the bump directly contacts to the connection feet. Through the aforementioned interposer structure, it is sufficient to achieve the purpose of improving the electrical performance of the semiconductor device and avoiding the signal being loss through the TSV.

    Abstract translation: 本发明涉及内插器结构及其制造方法。 插入器结构包括第一电介质层，导电焊盘和凸块。 所述导电焊盘设置在所述第一电介质层中，其中所述导电焊盘的顶表面从所述第一介电层的第一表面露出，所述导电焊盘还包括多个连接脚，并且所述连接脚从底部突出 导电焊盘的表面到第一介电层的第二表面。 凸块设置在第一电介质层的第二表面上，凸块直接接触连接脚。 通过上述插入器结构，达到提高半导体器件的电气性能并避免信号通过TSV损耗的目的就足够了。

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