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    Nonvolatile memory and manipulating method thereof
    23.
    发明授权
    Nonvolatile memory and manipulating method thereof 有权
    非易失性存储器及其操作方法

    公开(公告)号：US08837220B2

    公开(公告)日：2014-09-16

    申请号：US13741442

    申请日：2013-01-15

    Applicant: United Microelectronics Corp.

    Inventor： Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

    IPC: G11C11/34 ,  G11C16/14 ,  H01L27/088 ,  G11C16/10

    CPC classification number: G11C16/14 ,  G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/088 ,  H01L27/11565 ,  H01L27/11568

    Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

    Abstract translation: 提供了一种非易失性存储器的操作方法，包括以下步骤。 提供具有多个存储单元的非易失性存储器。 两个相邻的存储器单元对应于一个位，并且包括基板，第一和第二第一掺杂区域，第二掺杂区域，电荷俘获层，控制栅极，第一位线，源极线和与 第一个位线。 形成第一和第二通道。 电荷捕获层设置在第一和第二通道上。 通过以下步骤对相邻的两个存储单元进行编程。 第一正电压和负电压分别施加到第一和第二掺杂区域之间的控制栅极以及第二和第二掺杂区域之间的控制栅极。 第一个电压被施加到源极线。

    NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    24.
    发明申请
    NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    非易失性存储器结构及其制造方法

    公开(公告)号：US20140197472A1

    公开(公告)日：2014-07-17

    申请号：US13741399

    申请日：2013-01-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Chung Chang ,  Shen-De Wang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

    IPC: H01L29/66 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4234 ,  H01L29/792

    Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

    Abstract translation: 一种用于制造非易失性存储器结构的方法包括提供具有存储区域和限定在其上的逻辑区域的衬底，在形成存储区域中的至少第一栅极的同时屏蔽逻辑区域，形成氧化物 - 氧化物 - 氧化物（ONO ）结构，在衬底上形成覆盖ONO结构的氧化物结构，在逻辑区域中形成第二栅极的同时掩蔽存储区域，以及在第一栅极的侧壁上形成第一间隔物，在侧壁上形成第二间隔物 的第二个门。

    RRAM STRUCTURE AND FABRICATING METHOD OF THE SAME
    27.
    发明公开
    RRAM STRUCTURE AND FABRICATING METHOD OF THE SAME 审中-公开

    公开(公告)号：US20240081158A1

    公开(公告)日：2024-03-07

    申请号：US17950049

    申请日：2022-09-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei Cheng ,  ZHEN CHEN ,  Shen-De Wang

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/1233

    Abstract: An RRAM structure includes a dielectric layer. A bottom electrode, a resistive switching layer and a top electrode are disposed from bottom to top on the dielectric layer. A spacer is disposed at sidewalls of the bottom electrode, the resistive switching layer and the top electrode. The spacer includes an L-shaped spacer and a sail-shaped spacer. The L-shaped spacer contacts the sidewall of the bottom electrode, the sidewall of the resistive switching layer and the sidewall of the top electrode. The sail-shaped spacer is disposed on the L-shaped spacer. A metal line is disposed on the top electrode and contacts the top electrode and the spacer.

    SEMICONDUCTOR DEVICE
    28.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220310839A1

    公开(公告)日：2022-09-29

    申请号：US17227392

    申请日：2021-04-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Cheng-Hua Yang ,  Chih-Chien Chang ,  Shen-De Wang

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40

    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

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