公开(公告)号：US10665597B2

公开(公告)日：2020-05-26

申请号：US15949368

申请日：2018-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L27/112 ,  H01L23/525

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.

公开(公告)号：US20190115469A1

公开(公告)日：2019-04-18

申请号：US16102847

申请日：2018-08-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/324 ,  H01L21/762 ,  H01L21/265 ,  H01L21/308 ,  H01L27/02 ,  H01L29/06 ,  H01L29/36 ,  H01L29/08 ,  H01L29/423 ,  G03F1/36

Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

公开(公告)号：US09972539B2

公开(公告)日：2018-05-15

申请号：US15475097

申请日：2017-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

公开(公告)号：US20250072091A1

公开(公告)日：2025-02-27

申请号：US18465183

申请日：2023-09-12

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li ,  Shan-Shi Huang

IPC: H01L29/423

Abstract: Provided is a transistor structure including a gate, a gate dielectric layer, a source region and a drain region. The gate is disposed on a substrate. The gate dielectric layer is disposed between the gate and the substrate. The source region and the drain region are respectively disposed at two opposite sides of the gate. From a top view above the substrate, the gate has two opposite edges in a first direction intersecting a second direction where a channel length of the transistor structure is located, and each of the two opposite edges has a non-linear shape.

公开(公告)号：US20250015183A1

公开(公告)日：2025-01-09

申请号：US18895420

申请日：2024-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423

Abstract: A method of fabricating semiconductor device, the semiconductor device includes a substrate, a first transistor and a second transistor. The substrate includes a high-voltage region and a low-voltage region. The first transistor is disposed on the HV region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. The first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. The second transistor is disposed on the LV region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. The first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.

公开(公告)号：US20240274707A1

公开(公告)日：2024-08-15

申请号：US18645366

申请日：2024-04-24

Applicant: United Microelectronics Corp.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Che-Hua Chang

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7802 ,  H01L29/78618 ,  H01L29/7869

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.

公开(公告)号：US20230335637A1

公开(公告)日：2023-10-19

申请号：US18139960

申请日：2023-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung LI ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/0649 ,  H01L29/1079 ,  H01L29/517 ,  H01L29/66689

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US20230197843A1

公开(公告)日：2023-06-22

申请号：US17578383

申请日：2022-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Che-Hua Chang

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7802 ,  H01L29/7869 ,  H01L29/78618

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first concave top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.

公开(公告)号：US20230187547A1

公开(公告)日：2023-06-15

申请号：US17569527

申请日：2022-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Hua Chang ,  Shin-Hung Li ,  Tsung-Yu Yang ,  Ruei-Jhe Tsao

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L29/401 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66704

Abstract: A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.

公开(公告)号：US11640981B2

公开(公告)日：2023-05-02

申请号：US17347614

申请日：2021-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/265 ,  H01L21/28

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, two shallow trench isolation structures are located in the substrate, a first region, a second region and a third region are defined between the two shallow trench isolation structures, the second region is located between the first region and the third region. Two thick oxide layers are respectively located in the first region and the third region and directly contact the two shallow trench isolation structures respectively, and a thin oxide layer is located in the second region, the thickness of the thick oxide layer in the first region is greater than that of the thin oxide layer in the second region.