公开(公告)号：US09306045B2

公开(公告)日：2016-04-05

申请号：US14083551

申请日：2013-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Chung-Yi Chiu

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/08

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device.

Abstract translation: 提供了一种半导体功率器件，包括第一导电类型的衬底，形成在衬底上的第二导电类型的缓冲层，形成在缓冲层上的电压支撑层，以及形成在衬底上的不同导电类型的交替部分 。 电压支撑层包括第一导电类型的第一半导体区域和第二导电类型的第二半导体区域，其中第一半导体区域和第二半导体区域交替布置。 交替部分和缓冲层形成交替导电类型的分段结构，其用作半导体器件的阳极。

公开(公告)号：US20200381431A1

公开(公告)日：2020-12-03

申请号：US16995941

申请日：2020-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US10784261B2

公开(公告)日：2020-09-22

申请号：US16697800

申请日：2019-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L27/14 ,  H01L27/146 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US20180277679A1

公开(公告)日：2018-09-27

申请号：US15985683

申请日：2018-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Hsin-Che Huang ,  Shyan-Liang Chou ,  Hung-Lin Shih

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649

Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.

公开(公告)号：US20180269107A1

公开(公告)日：2018-09-20

申请号：US15458038

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yat-Kai Sun ,  Chao-Nan Chen ,  Hung-Lin Shih ,  Che-Hung Huang ,  Wei-Lun Hsu ,  Cheng-Chia Liu

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.

公开(公告)号：US10079180B1

公开(公告)日：2018-09-18

申请号：US15458038

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yat-Kai Sun ,  Chao-Nan Chen ,  Hung-Lin Shih ,  Che-Hung Huang ,  Wei-Lun Hsu ,  Cheng-Chia Liu

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.

公开(公告)号：US09530696B1

公开(公告)日：2016-12-27

申请号：US14921514

申请日：2015-10-23

Applicant: United Microelectronics Corp.

Inventor： Wei-Hsin Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Wei-Lun Hsu ,  Shang-Yi Yang ,  Pi-Hsuan Lai

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成有多个牺牲栅极和其下的多个牺牲栅介质层。 在牺牲栅极之间填充层间电介质层。 在层间电介质层上形成保护层。 去除牺牲栅极和牺牲栅极电介质层以形成开口，其中层间介电层被保护层保护而不被凹陷。 在开口中形成堆叠的栅极结构，其中保护层被去除。