公开(公告)号：US20170154887A1

公开(公告)日：2017-06-01

申请号：US15432165

申请日：2017-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US09305994B2

公开(公告)日：2016-04-05

申请号：US14445416

申请日：2014-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/60

Abstract: A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.

Abstract translation: 提供了包括堆叠电容结构的半导体装置。 堆叠的电容结构包括具有与第一内金属层的边缘相邻的第一焊盘区域的第一内部金属层，设置在第一内部金属层上并暴露第一焊盘区域的第一绝缘层，设置的第二内部金属层 在第一绝缘层上并且具有与第二内金属层的边缘相邻的第二焊盘区域，设置在第二内金属层上并暴露第二焊盘区域的第二绝缘层，以及覆盖第二内金属层的第三内金属层 金属层并且包括至少一个第一狭缝。 第一焊盘区域和第二焊盘区域包括多个焊盘。 第一狭缝对应于第二焊盘区域，使得第二焊盘区域上的焊盘露出。

公开(公告)号：US20150264813A1

公开(公告)日：2015-09-17

申请号：US14204898

申请日：2014-03-11

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  H05K1/16 ,  H05K1/11

CPC classification number: H05K1/162 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5223 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4673 ,  H05K2201/0179 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2201/10378

Abstract: A chip-stack interposer structure including a passive device is described, including an interposing layer, a capacitor, a first contact and a second contact. The capacitor is embedded in or disposed on the interposing layer, including a first electrode, a second electrode and a dielectric layer between the first and the second electrodes. The first contact is connected with the first electrode. The second contact is connected with the second electrode. The first electrode and the second electrode are disposed at the same side of the interposing layer or at different sides of the interposing layer.

Abstract translation: 描述包括无源器件的芯片堆叠插入器结构，包括中介层，电容器，第一接触和第二接触。 电容器嵌入或设置在插入层上，包括在第一和第二电极之间的第一电极，第二电极和介电层。 第一触点与第一电极连接。 第二触点与第二电极连接。 第一电极和第二电极设置在插入层的相同侧或者插入层的不同侧。

公开(公告)号：US20240347459A1

公开(公告)日：2024-10-17

申请号：US18317117

申请日：2023-05-15

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Ding Lung Chen

IPC: H01L23/528

CPC classification number: H01L23/5286

Abstract: Provided is a semiconductor including a substrate, a semiconductor element disposed on the substrate, an interconnect structure, first and second power deliver lines, and first and second power deliver network (PDN) structures. The interconnect structure is disposed in the element region, above the semiconductor element, and electrically connected with the semiconductor element. The first and the second power deliver lines are disposed above the interconnect structure and electrically connected to the first and the second power supplies, respectively. The first PDN structure is disposed between the substrate and the first power deliver line, and connected to the first power deliver line and a lowest circuit layer of the interconnect structure. The second PDN structure is disposed between the substrate and the second power deliver line, and connected to the second power deliver line and the lowest circuit layer of the interconnect structure.

公开(公告)号：US20210335654A1

公开(公告)日：2021-10-28

申请号：US16884081

申请日：2020-05-27

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L21/768 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

公开(公告)号：US10134836B2

公开(公告)日：2018-11-20

申请号：US15476751

申请日：2017-03-31

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L23/535 ,  H01L21/84 ,  H01L29/66 ,  H01L49/02

Abstract: A semiconductor device and a method of fabricating the same are provide. The fabricating method includes providing a silicon-on-insulator (SOI) substrate that includes, from bottom to top, a substrate, a first insulating layer and a semiconductor layer. The semiconductor layer is patterned to form a plurality of dummy patterns. A second insulating layer is formed around the plurality of dummy patterns. The plurality of dummy patterns are removed to form a plurality of openings. A dielectric structure is formed on the substrate and fills into the plurality of openings.

公开(公告)号：US20180219063A1

公开(公告)日：2018-08-02

申请号：US15476751

申请日：2017-03-31

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L49/02 ,  H01L23/535 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L29/0649 ,  H01L21/76289 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L28/10 ,  H01L29/66545

Abstract: A semiconductor device and a method of fabricating the same are provide. The fabricating method includes providing a silicon-on-insulator (SOI) substrate that includes, from bottom to top, a substrate, a first insulating layer and a semiconductor layer. The semiconductor layer is patterned to form a plurality of dummy patterns. A second insulating layer is formed around the plurality of dummy patterns. The plurality of dummy patterns are removed to form a plurality of openings. A dielectric structure is formed on the substrate and fills into the plurality of openings.

公开(公告)号：US09991171B1

公开(公告)日：2018-06-05

申请号：US15793822

申请日：2017-10-25

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L29/51 ,  H01L29/40 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/823462 ,  H01L21/02172 ,  H01L21/76879 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/516 ,  H01L29/7832 ,  H01L29/78391

Abstract: A semiconductor device and an integrated circuit are provided. The semiconductor device includes a field effect transistor, a negative capacitor and a control circuit, which are disposed at different horizontal levels on a substrate. The field effect transistor includes a front gate, a back gate and an oxide semiconductor layer disposed between the front gate and the back gate. The negative capacitor is electrically connected to the back gate of the field effect transistor. The negative capacitor includes a pair of electrodes and a ferroelectric material layer disposed between the pair of electrodes. The negative capacitor is electrically connected between the back gate of the field effect transistor and the control circuit, the control circuit is configured to charge the negative capacitor and to asses a voltage between the pair of electrodes of the negative capacitor.

公开(公告)号：US09893066B2

公开(公告)日：2018-02-13

申请号：US15432165

申请日：2017-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/49 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US20170125599A1

公开(公告)日：2017-05-04

申请号：US14960041

申请日：2015-12-04

Applicant: United Microelectronics Corp.

Inventor： Hai-Biao Yao ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Zhi-Biao Zhou

IPC: H01L29/786 ,  H01L29/51 ,  H01L21/033 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02565 ,  H01L21/0332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78696

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.