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    Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply
    21.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply 有权
    节能和节能的方法，装置和系统，包括通过使用寄存器二次不间断电源提高处理器核心深度掉电退出延迟

    公开(公告)号：US08819461B2

    公开(公告)日：2014-08-26

    申请号：US13335880

    申请日：2011-12-22

    Applicant: Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev s. Jahagirdar ,  Varghese George

    Inventor： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev s. Jahagirdar ,  Varghese George

    IPC: G06F1/00

    CPC classification number: G06F1/3296 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D10/172

    Abstract: Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.

    Abstract translation: 本发明的实施例涉及从计算设备处理器核心深度掉电来改善退出等待时间。 处理器状态数据可以在深度掉电模式期间通过提供第二不间断电压供应来始终保持驻留在处理器的关键状态寄存器内的保持器电路。 当这些寄存器接收到指示处理器电源状态将从活动处理器电源状态降低到零处理器电源状态的控制信号时，它们将临界状态数据从临界状态寄存器锁存器写入到所提供的保持器电路 不间断的电源。 然后，当寄存器接收到指示处理器的处理器电源状态将增加回到活动处理器功率状态的控制信号时，存储在保持器电路中的临界状态数据被写回到临界状态寄存器锁存器。

    Method, apparatus and system to dynamically choose an optimum power state
    30.
    发明申请
    Method, apparatus and system to dynamically choose an optimum power state 有权
    方法，装置和系统动态选择最佳功率状态

    公开(公告)号：US20070157042A1

    公开(公告)日：2007-07-05

    申请号：US11322606

    申请日：2005-12-30

    Applicant: Sanjeev Jahagirdar ,  Varghese George ,  Jose Allarey ,  Eric Heit

    Inventor： Sanjeev Jahagirdar ,  Varghese George ,  Jose Allarey ,  Eric Heit

    IPC: G06F1/32

    CPC classification number: G06F1/3203

    Abstract: Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.

    Abstract translation: 本发明的一些实施例包括用于动态选择最佳功率状态的装置和方法。 在一些实施例中，最佳功率状态可以根据关于各种功率状态的历史信息来确定，该装置或装置的任何实施例装备有该方法的装置或操作实施例的实施例可能会遇到。 一些实施例可以生成寄存器来维护关于各种功率状态的信息。 在一些实施例中，功率管理逻辑可以基于该信息来确定最佳功率状态。 描述其他实施例。

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