Inverter, method of manufacturing the same, and logic circuit including the inverter
    22.
    发明授权
    Inverter, method of manufacturing the same, and logic circuit including the inverter 有权
    逆变器及其制造方法以及包括逆变器的逻辑电路

    公开(公告)号:US07977978B2

    公开(公告)日:2011-07-12

    申请号:US12591654

    申请日:2009-11-25

    IPC分类号: H03K19/00

    摘要: Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

    摘要翻译: 提供逆变器,逆变器的制造方法以及包括逆变器的逻辑电路。 反相器可以包括具有不同沟道层结构的第一晶体管和第二晶体管。 第一晶体管的沟道层可以包括下层和上层,并且第二晶体管的沟道层可以与下层和上层之一相同。 下层和上层中的至少一层可以是氧化物层。 逆变器可以是增强/耗尽型(E / D)型逆变器或互补型逆变器。

    Ferroelectric capacitor having three-dimensional structure, nonvolatile memory device having the same and method of fabricating the same
    23.
    发明授权
    Ferroelectric capacitor having three-dimensional structure, nonvolatile memory device having the same and method of fabricating the same 失效
    具有三维结构的铁电电容器,具有相同的非易失性存储器件及其制造方法

    公开(公告)号:US07910967B2

    公开(公告)日:2011-03-22

    申请号:US11515024

    申请日:2006-09-05

    CPC分类号: H01L27/11502 H01L27/11507

    摘要: A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.

    摘要翻译: 提供具有三维结构的铁电电容器,具有其的非易失性存储器件及其制造方法。 铁电电容器可以包括沟槽型下电极,形成在下电极周围的至少一层,形成在下电极和至少一层上的铁电层(PZT层)和形成在铁电层上的上电极。 所述至少一个层可以是至少一个绝缘夹层,并且所述至少一个层也可以是至少一个扩散阻挡层。 所述至少一层可以由除了SiO2之外的绝缘材料形成,或者可以具有不包括Pb的钙钛矿晶体结构。

    Thin film transistor and method of manufacturing the same
    26.
    发明申请
    Thin film transistor and method of manufacturing the same 审中-公开
    薄膜晶体管及其制造方法

    公开(公告)号:US20080277663A1

    公开(公告)日:2008-11-13

    申请号:US11984072

    申请日:2007-11-13

    IPC分类号: H01L29/10 H01L21/84

    CPC分类号: H01L29/7869 H01L29/78606

    摘要: Provided is a thin film transistor that includes a substrate on which an insulating layer is formed, a gate formed on a region of the insulating layer, a gate insulating layer formed on the insulating layer and the gate, a channel region formed on the gate insulating layer on a region corresponding to the location of the gate, a source and a drain respectively formed by contacting either side of the channel region; and a passivation layer formed of a compound made of a group II element and a halogen element on the channel region.

    摘要翻译: 提供一种薄膜晶体管,其包括其上形成有绝缘层的基板,形成在绝缘层的区域上的栅极,形成在绝缘层上的栅极绝缘层和栅极,形成在栅极绝缘上的沟道区域 在对应于栅极的位置的区域上分别形成一个源极和漏极,该漏极和漏极分别通过与沟道区域的任一侧接触; 以及由沟道区域上由II族元素和卤素元素制成的化合物形成的钝化层。

    Thin film transistor and display panel employing the same
    27.
    发明授权
    Thin film transistor and display panel employing the same 有权
    薄膜晶体管和采用其的显示面板

    公开(公告)号:US09178030B2

    公开(公告)日:2015-11-03

    申请号:US13616964

    申请日:2012-09-14

    摘要: A thin film transistor is provided. The transistor includes a gate; a first passivation layer covering the gate; a channel layer disposed on the first passivation layer; a source and a drain that are disposed on the first passivation layer and contact two sides of the channel layer; a second passivation layer covering the channel layer, the source, and the drain; first and second transparent electrode layers that are disposed on the second passivation layer and spaced apart from each other; a first transparent conductive via that penetrates the second passivation layer and connects the source and the first transparent electrode layer; and a second transparent conductive via that penetrates the second passivation layer and connects the drain and the second transparent electrode layer. A cross-sectional area of the gate is larger than a cross-sectional area of the channel layer, the source, and the drain combined.

    摘要翻译: 提供薄膜晶体管。 晶体管包括一个栅极; 覆盖所述栅极的第一钝化层; 设置在所述第一钝化层上的沟道层; 源极和漏极,其设置在所述第一钝化层上并接触所述沟道层的两侧; 覆盖沟道层,源极和漏极的第二钝化层; 第一和第二透明电极层,其设置在第二钝化层上并彼此间隔开; 第一透明导电通孔,其穿透所述第二钝化层并连接所述源极和所述第一透明电极层; 以及第二透明导电通孔,其穿透第二钝化层并连接漏极和第二透明电极层。 栅极的横截面面积大于沟道层,源极和漏极组合的横截面面积。

    CMOS image sensor and method of manufacturing the same
    28.
    发明授权
    CMOS image sensor and method of manufacturing the same 有权
    CMOS图像传感器及其制造方法

    公开(公告)号:US08507906B2

    公开(公告)日:2013-08-13

    申请号:US12591909

    申请日:2009-12-04

    IPC分类号: H01L31/032 H01L21/00

    摘要: Provided is a complementary metal oxide semiconductor (CMOS) image sensor having a structure capable of increasing areas of photodiodes in unit pixels and expanding light receiving areas of the photodiodes. In the CMOS image sensor, transfer transistors may be formed on the photodiode, and reset transistors, source follower transistors, and selection transistors may be formed on a layer on which the transfer transistors are not formed. In such a CMOS image sensor, the areas of the photodiodes may be increased in unit pixels so that a size of the unit pixels may be reduced and sensitivity of the pixel may be improved.

    摘要翻译: 提供了具有能够增加单位像素中的光电二极管的面积并扩大光电二极管的光接收面积的结构的互补金属氧化物半导体(CMOS)图像传感器。 在CMOS图像传感器中,可以在光电二极管上形成传输晶体管,并且可以在不形成传输晶体管的层上形成复位晶体管,源极跟随器晶体管和选择晶体管。 在这样的CMOS图像传感器中,可以以单位像素增加光电二极管的面积,从而可以减小单位像素的尺寸,并且可以提高像素的灵敏度。

    HIGH-VOLTAGE OXIDE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    29.
    发明申请
    HIGH-VOLTAGE OXIDE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    高电压氧化物晶体管及其制造方法

    公开(公告)号:US20130168770A1

    公开(公告)日:2013-07-04

    申请号:US13547200

    申请日:2012-07-12

    IPC分类号: H01L29/772 H01L21/336

    摘要: A high-voltage oxide transistor includes a substrate; a channel layer disposed on the substrate; a gate electrode disposed on the substrate to correspond to the channel layer; a source contacting a first side of the channel layer; and a drain contacting a second side of the channel layer, wherein the channel layer includes a plurality of oxide layers, and none of the plurality of oxide layers include silicon. The gate electrode may be disposed on or under the channel layer. Otherwise, the gate electrodes may be disposed respectively on and under the channel layer.

    摘要翻译: 高压氧化物晶体管包括基板; 设置在所述基板上的沟道层; 设置在所述基板上以对应于所述沟道层的栅电极; 源极,与所述沟道层的第一侧接触; 以及与沟道层的第二面接触的漏极,其中所述沟道层包括多个氧化物层,并且所述多个氧化物层中没有一个包括硅。 栅电极可以设置在沟道层上或下面。 否则,栅极电极可以分别设置在沟道层上和下面。