公开(公告)号：US20060245118A1

公开(公告)日：2006-11-02

申请号：US11476004

申请日：2006-06-28

Applicant: Mark Tuttle

Inventor： Mark Tuttle

IPC: G11B5/187

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  H01F10/3254 ,  H01F10/3268 ,  H01F41/308 ,  H01L27/222 ,  H01L43/08 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T428/1114 ,  Y10T428/1121

Abstract: A method of forming a magnetic tunnel junction memory element and the resulting structure are disclosed. A magnetic tunnel junction memory element comprising a thick nonmagnetic layer between two ferromagnetic layers. The thick nonmagnetic layer has an opening in which a thinner tunnel barrier layer is disposed. The resistance of a magnetic tunnel junction memory element may be controlled by adjusting the surface area and/or thickness of the tunnel barrier layer without regard to the surface area of the ferromagnetic layers.

公开(公告)号：US20060077704A1

公开(公告)日：2006-04-13

申请号：US11286918

申请日：2005-11-23

Applicant: Mark Tuttle ,  D. Durcan

Inventor： Mark Tuttle ,  D. Durcan

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5006

Abstract: An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated circuit includes supporting a sensor in the integrated circuit and using the sensor to sense environmental data.

Abstract translation: 集成电路包括操作电路; 被配置为感测环境参数的传感器; 以及耦合到所述传感器和所述操作电路并被配置为影响所述操作电路以至少部分抵消所述环境参数的影响的调节电路。 一种测试集成电路的方法包括在集成电路中支持传感器，并使用传感器来感测环境数据。

公开(公告)号：US20060019422A1

公开(公告)日：2006-01-26

申请号：US11233665

申请日：2005-09-23

Applicant: Mark Tuttle ,  James Deak

Inventor： Mark Tuttle ,  James Deak

IPC: H01L21/00

CPC classification number: H01L23/552 ,  H01L23/3107 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  Y10S257/921 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Structures and methods for providing magnetic shielding for integrated circuits are disclosed. The shielding comprises a foil or sheet of magnetically permeable material applied to an outer surface of a molded (e.g., epoxy) integrated circuit package. The foil can be held in place by adhesive or by mechanical means. The thickness of the shielding can be tailored to a customer's specific needs, and can be applied after all high temperature processing, such that a degaussed shield can be provided despite use of strong magnetic fields during high temperature processing, which fields are employed to maintain pinned magnetic layers within the integrated circuit.

公开(公告)号：US20050190620A1

公开(公告)日：2005-09-01

申请号：US11123916

申请日：2005-05-06

Applicant: Mirmajid Seyyedy ,  Mark Tuttle ,  Glen Hush

Inventor： Mirmajid Seyyedy ,  Mark Tuttle ,  Glen Hush

IPC: G11C11/15 ,  G11C17/16 ,  G11C7/00

CPC classification number: H01L27/222 ,  G11C11/005 ,  G11C11/15 ,  G11C17/16 ,  G11C17/165 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.

公开(公告)号：US06664613B2

公开(公告)日：2003-12-16

申请号：US10285554

申请日：2002-11-01

Applicant: Mark Tuttle

Inventor： Mark Tuttle

IPC: H01L23552

CPC classification number: H05K1/0233 ,  H01L23/552 ,  H01L23/585 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01025 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  H01L2224/0401

Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.

公开(公告)号：US06559521B2

公开(公告)日：2003-05-06

申请号：US10115960

申请日：2002-04-05

Applicant: Mark Tuttle

Inventor： Mark Tuttle

IPC: H01L23552

CPC classification number: H05K1/0233 ,  H01L23/552 ,  H01L23/585 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01025 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  H01L2224/0401

Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.

Abstract translation: 公开了一种为包含电磁电路元件的集成电路芯片提供一个或多个电磁屏蔽层的方法和装置。 屏蔽层可以与集成电路芯片接触，包括诸如MRAM的磁存储器结构，或者在倒装芯片载体中，或者两者。 支撑芯片的印刷电路板也可以具有一个或多个屏蔽层。

公开(公告)号：US09324690B2

公开(公告)日：2016-04-26

申请号：US13361183

申请日：2012-01-30

Applicant: Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H05K3/36 ,  H01L25/065 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01004 ,  H01L2924/15311 ,  Y10T29/49165

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Abstract translation: 一些实施例包括装置，系统和方法，其具有底座，第一管芯，第二管芯，第二管芯和第二管芯，第二管芯和第二管芯和第二管芯，第二管芯和第二管芯， 被配置为在所述基座与所述第一和第二骰子中的至少一个之间传送信号。

公开(公告)号：US20130036606A1

公开(公告)日：2013-02-14

申请号：US13361183

申请日：2012-01-30

Applicant: Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H01K3/10

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01004 ,  H01L2924/15311 ,  Y10T29/49165

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Abstract translation: 一些实施例包括装置，系统和方法，其具有底座，第一管芯，第二管芯，第二管芯和第二管芯，第二管芯和第二管芯和第二管芯，第二管芯和第二管芯， 被配置为在所述基座与所述第一和第二骰子中的至少一个之间传送信号。

公开(公告)号：US08106520B2

公开(公告)日：2012-01-31

申请号：US12209052

申请日：2008-09-11

Applicant: Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01004 ,  H01L2924/15311 ,  Y10T29/49165

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Abstract translation: 一些实施例包括装置，系统和方法，其具有底座，第一管芯，第二管芯，第二管芯和第二管芯，第二管芯和第二管芯和第二管芯，第二管芯和第二管芯， 被配置为在所述基座与所述第一和第二骰子中的至少一个之间传送信号。

公开(公告)号：US07271611B2

公开(公告)日：2007-09-18

申请号：US11698678

申请日：2007-01-26

Applicant: Warren M. Farnworth ,  Mark Tuttle

Inventor： Warren M. Farnworth ,  Mark Tuttle

IPC: G01R31/26

CPC classification number: G01R31/2886

Abstract: A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.

Abstract translation: 用于测试半导体部件的方法包括以下步骤：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将该互连件与部件分离。 接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。 在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。 互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。 系统包括互连，用于将衬底对准互连的对准系统，用于将组件粘合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。