摘要:
The present invention provides a semiconductor device package comprising a substrate with at lease a pre-formed die receiving cavity formed and terminal contact metal pads formed within an upper surface of the substrate. At lease a first die is disposed within the die receiving cavity. A first dielectric layer is formed on the first die and the substrate and refilled into a gap between the first die and the substrate to absorb thermal mechanical stress there between. A first re-distribution layer (RDL) is formed on the first dielectric layer and coupled to the first die. A second dielectric layer is formed on the first RDL, and then a second die is disposed on the second dielectric layer and surrounded by core pastes having through holes thereon. A second re-distribution layer (RDL) is formed on the core pastes to fill the through holes, and then a third dielectric layer formed on the second RDL.
摘要:
The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance.
摘要:
A transmission mechanism with intermittent output movement includes an output shaft rotatably mounted to first and second cams and a sun gear mounted to the output shaft. A first rocker includes a first planet gear meshed with the sun gear and first and second rollers rotatably mounted on opposite sides of the first planet gear and respectively in contact with the first and second cams. A second rocker includes a second planet gear meshed with the sun gear. An end of a first connecting rod is mounted to the first rocker. An end of a second connecting rod is mounted to the second rocker. Two ends of a link are rotatably mounted to the other ends of the first and second connecting rods. A planet gear carrier is mounted to an input shaft coaxial to the input shaft and includes an end rotatably mounted to the first rocker.
摘要:
A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.
摘要:
An ultra cycling nitride read only memory (NROM) device is coupled to a NROM array such that both bits of the ultra cycling NROM device will be erased when all NROM devices of the NROM array are erased. The ultra cycling NROM device is then programmed at its right bit. A threshold voltage difference will be obtained for the ultra cycling NROM device for the un-programmed left bit. Next, a cycling number is obtained based on the threshold voltage difference for the ultra cycling NROM device. A threshold voltage shift can be found based on the cycling number for the NROM array. Finally, an erase voltage will be calculated according to the threshold voltage shift for the NROM array. If the NROM array is programmed again, the erase voltage will be applied to un-programmed NROM devices of the NROM array to further reduce the threshold voltages.
摘要:
A system and a method for controlling a sensorless motor are disclosed, where the system includes a motor driver and a zero-crossing detector. The motor driver can drive the sensorless motor. The zero-crossing detector can detect a zero-crossing point when the voltage of one motor coil of the sensorless motor is in a blanking period.
摘要:
A voltage-boosting generator for reducing the effects due to operating voltage variation and temperature change. The generator comprises a delay line circuit and a voltage boosting circuit. The delay line circuit is used to perform a time delay according to an initial boosting signal and to produce a control signal. The voltage boosting circuit is used to boosted voltage according to the control signal.
摘要:
An apparatus and a method for detecting a lock error in a sensorless motor are disclosed, where the apparatus includes a multiplexer, a negative booster, a comparator and a timer. The multiplexer can receive a coil voltage from the sensorless motor. The negative booster can receive a neutralizing voltage from the sensorless motor and drop the neutralizing voltage. The comparator can compare the coil voltage with the dropped neutralizing voltage for outputting a zero-crossing signal. The timer can count time duration during the zero-crossing signal maintained at the a logic level and determine the lock error in the sensorless motor when the time duration exceeds a predetermined period.
摘要:
An apparatus and a method for driving a sensorless motor are described and shown in the specification and drawings, where the method includes steps as follows. First, a control signal is acquired, where the control signal has information of a predetermined rotational speed. Next, energy is supplied and progressively increased to the sensorless motor, so as to rotate a rotor of the sensorless motor. Then, a position of the rotor is detected. Finally, the energy is gradually regulated so that the sensorless motor is maintained at the predetermined rotational speed.
摘要:
A high-side driving circuit is provided, where Q terminal and Q terminal of the latch circuit respectively feed back to the first switch and the second switch, which may control asymmetric impedance, such that the high-side driving circuit can prevent noise.