公开(公告)号：US20080197469A1

公开(公告)日：2008-08-21

申请号：US11708475

申请日：2007-02-21

申请人： Wen-Kun Yang ,  Hsien-Wen Hsu ,  Ya-Tzu Wu ,  Ching-Shun Huang

发明人： Wen-Kun Yang ,  Hsien-Wen Hsu ,  Ya-Tzu Wu ,  Ching-Shun Huang

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01055

摘要： The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance.

摘要翻译： 本发明提供了一种多芯片封装的结构及其方法，其包括在衬底的上表面内形成有预成型的模具容纳空腔的衬底。 通过粘合将芯片设置在模具接收腔内，并且将弹性介电层填充到模具和基板之间的间隙中以吸收热机械应力; 因此，封装的厚度减小，结构的CTE失配减小。 本发明还提供了具有更高可靠性和更低制造成本的SIP的结构。 该过程更简单，并且比传统的更容易形成多芯片封装。 因此，本发明公开了一种具有减小厚度和良好CTE匹配性能的扇出WLP。

公开(公告)号：US20090212428A1

公开(公告)日：2009-08-27

申请号：US12035559

申请日：2008-02-22

申请人： Wen-Kun Yang ,  Ya-Tzu Wu ,  Cheng-Chieh Tai

发明人： Wen-Kun Yang ,  Ya-Tzu Wu ,  Cheng-Chieh Tai

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L23/525 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/01028 ,  H01L2924/01022 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A conductive line structure of a semiconductor device, the structure comprising a substrate having bonding pad; a first dielectric layer formed over the substrate; a solder pad formed over the first dielectric layer; a buffer scheme formed over the first dielectric layer and between the bonding pad and the solder pad; a conductive line formed over the buffer scheme for coupling between the bonding pad and the solder pad; a second dielectric layer formed over the conductive line to expose the solder pad; and a solder ball formed over the solder pad.

摘要翻译： 一种半导体器件的导线结构，该结构包括具有接合焊盘的衬底; 形成在所述基板上的第一电介质层; 形成在所述第一电介质层上的焊料焊盘; 形成在所述第一电介质层上并且在所述焊盘和所述焊盘之间的缓冲方案; 形成在用于在焊盘和焊盘之间耦合的缓冲方案的导电线; 形成在所述导线上以露出所述焊盘的第二电介质层; 以及形成在焊盘上的焊球。

公开(公告)号：US20090127686A1

公开(公告)日：2009-05-21

申请号：US11984781

申请日：2007-11-21

申请人： Wen-Kun Yang ,  Chi-Yu Wang ,  Hsien-Wen Hsu

发明人： Wen-Kun Yang ,  Chi-Yu Wang ,  Hsien-Wen Hsu

IPC分类号： H01L23/488 ,  H01L21/58

CPC分类号： H01L24/82 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer.

摘要翻译： 本发明公开了一种用于半导体器件的第一多管芯封装结构，该结构包括具有管接收窗口和形成在其中的互连通孔的衬底; 第一级半导体管芯，其通过背对背方案形成在第二级半导体管芯下方并且在管芯接收窗内，其中第一多管芯封装包括形成在第一级半导体管芯下方的第一级接触焊盘，其具有第一级构建 形成在其下方以耦合到第一级半导体管芯的第一焊盘; 形成在所述第二级半导体管芯上的第二级接触焊盘，其上形成有第二级构建层，以耦合到所述第二级半导体管芯的第二接合焊盘; 以及形成在第一层建立层下面的导电凸块。

公开(公告)号：US20090096093A1

公开(公告)日：2009-04-16

申请号：US11939732

申请日：2007-11-14

申请人： Wen-Kun Yang ,  Hsien-Wen Hsu

发明人： Wen-Kun Yang ,  Hsien-Wen Hsu

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5389 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers.

摘要翻译： 用于半导体管芯组件的互连结构包括其上形成有RDL的堆积层，形成在其上形成有管芯焊盘的管芯上，其中RDL耦合到管芯焊盘; 隔离基座，其具有附接在所述积层层上的球形开口以暴露所述积层内的球垫; 以及导电球，其放置在隔离基座的球形开口中并附着在积层内的球垫上。

公开(公告)号：US20080230884A1

公开(公告)日：2008-09-25

申请号：US11725827

申请日：2007-03-19

申请人： Wen-Kun Yang ,  Diann-Fang Lin ,  Tung-Chuan Wang ,  Hsien-Wen Hsu ,  Chih-Ming Chen

发明人： Wen-Kun Yang ,  Diann-Fang Lin ,  Tung-Chuan Wang ,  Hsien-Wen Hsu ,  Chih-Ming Chen

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/04 ,  H01L23/52

CPC分类号： H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate. A build up layer is form on the lower surface of substrate and the back side of first and second die.

摘要翻译： 本发明提供一种具有并排配置的多芯片的半导体器件封装，包括：具有通孔的基板，其中，所述基板具有通孔，连接通孔结构和上表面上的第一接触焊盘;以及第二接触焊盘， 基质。 具有第一接合焊盘的第一管芯和具有第二接合焊盘的第二管芯分别设置在管芯接收通孔内。 第一粘合材料形成在第一模具和第二模具和基板之下，并且第二粘合材料填充在第一和第二模具之间的间隙中以及接收基板的贯穿孔的模具的侧壁。 此外，形成接合线以在第二接合焊盘和第一接触焊盘之间在第一接合焊盘和第一接触焊盘之间耦合。 在接合线，第一和第二管芯和基板上形成介电层。 在基板的下表面和第一和第二模具的背面上形成堆积层。

公开(公告)号：US20080136004A1

公开(公告)日：2008-06-12

申请号：US11608404

申请日：2006-12-08

申请人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

发明人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00012

摘要： To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.

摘要翻译： 在第二个芯片的基座上选择和放置标准的第一个芯片尺寸封装，以获得比原始芯片尺寸封装更适合的堆叠芯片尺寸封装。 封装结构具有比传统堆叠封装尺寸更大的芯片尺寸封装。 此外，倒装芯片封装的端子引脚可以位于LGA封装的外围或BGA封装的阵列上。

公开(公告)号：US07525185B2

公开(公告)日：2009-04-28

申请号：US11725827

申请日：2007-03-19

申请人： Wen-Kun Yang ,  Diann-Fang Lin ,  Tung-Chuan Wang ,  Hsien-Wen Hsu ,  Chih-Ming Chen

发明人： Wen-Kun Yang ,  Diann-Fang Lin ,  Tung-Chuan Wang ,  Hsien-Wen Hsu ,  Chih-Ming Chen

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate. A build up layer is form on the lower surface of substrate and the back side of first and second die.

摘要翻译： 本发明提供一种具有并排配置的多芯片的半导体器件封装，包括：具有通孔的基板，其中，所述基板具有通孔，连接通孔结构和上表面上的第一接触焊盘;以及第二接触焊盘， 基质。 具有第一接合焊盘的第一管芯和具有第二接合焊盘的第二管芯分别设置在管芯接收通孔内。 第一粘合材料形成在第一模具和第二模具和基板之下，并且第二粘合材料填充在第一和第二模具之间的间隙中以及接收基板的贯穿孔的模具的侧壁。 此外，形成接合线以在第二接合焊盘和第一接触焊盘之间在第一接合焊盘和第一接触焊盘之间耦合。 在接合线，第一和第二管芯和基板上形成介电层。 在基板的下表面和第一和第二模具的背面上形成堆积层。

公开(公告)号：US20080265462A1

公开(公告)日：2008-10-30

申请号：US11739218

申请日：2007-04-24

申请人： Wen-Kun Yang ,  Hsien-Wen Hsu ,  Ming-Chung Cheng

发明人： Wen-Kun Yang ,  Hsien-Wen Hsu ,  Ming-Chung Cheng

IPC分类号： H01L21/56

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L24/96 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： The present invention provides an apparatus and a method for panel/wafer molding. The present invention discloses a base with a first separation layer, an upper molding base with a second separation layer, a cheap molding layer and a vacuum panel bonding machine for bonding, a curing unit, a cleaning unit and a separating unit; wherein upper molding base is rectangular or round. Therefore the present invention providing a simple, cheap universal panel/wafer molding apparatus for a round or rectangular type panel, and does no harm to the chip active surface.

摘要翻译： 本发明提供一种用于面板/晶片成型的装置和方法。 本发明公开了一种具有第一分离层的基底，具有第二分离层的上部模制基底，廉价的模制层和用于粘合的真空面板粘合机，固化单元，清洁单元和分离单元; 其中上成型基座为矩形或圆形。 因此，本发明提供了一种用于圆形或矩形型面板的简单，便宜的通用面板/晶片模制装置，并且对芯片活性表面没有任何损害。

公开(公告)号：US20080173792A1

公开(公告)日：2008-07-24

申请号：US11656410

申请日：2007-01-23

申请人： Wen-Kun Yang ,  Jui-Hsien Chang ,  Tung-chuan Wang ,  Chihwei Lin ,  Hsien-Wen Hsu

发明人： Wen-Kun Yang ,  Jui-Hsien Chang ,  Tung-chuan Wang ,  Chihwei Lin ,  Hsien-Wen Hsu

IPC分类号： H01L27/00

CPC分类号： H01L27/14618 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14625 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/19105 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00

摘要： The present invention provides an image sensor module structure comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate and a die having a micro lens disposed within the die receiving cavity. A dielectric layer is formed on the die and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.

摘要翻译： 本发明提供了一种图像传感器模块结构，其包括具有形成在基板的上表面内的模具接收空腔的基板和基板内的导电迹线以及具有设置在模具接收腔内的微透镜的模具。 在管芯和衬底上形成电介质层，在电介质层上形成再分配导电层（RDL），其中RDL耦合到管芯，并且导电迹线和电介质层具有露出 微透镜。 透镜保持器附接在基板上，并且透镜保持器具有安装在透镜保持器的上部的透镜。 滤光片安装在透镜和微透镜之间。 该结构还包括在透镜保持器内的衬底的上表面上的无源器件。

公开(公告)号：US20070072338A1

公开(公告)日：2007-03-29

申请号：US11235484

申请日：2005-09-26

申请人： Wen-Kun Yang ,  Chun Yu ,  Jui-Hsien Chang ,  Hsien-Wen Hsu

发明人： Wen-Kun Yang ,  Chun Yu ,  Jui-Hsien Chang ,  Hsien-Wen Hsu

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2924/00

摘要： The present invention provides a semiconductor device package singulation method. The method comprises printing a photo epoxy layer on the back surface of a substrate of a wafer for marking the scribe lines to be diced. Then etching is performed through the substrate along the marks in the photo epoxy layer. Dicing the panel into individual package with a typical art designing knife, the step not only avoids the roughness on the edge of each die, but also decrease the cost of singulation process.

摘要翻译： 本发明提供一种半导体器件封装分割方法。 该方法包括在晶片的基板的背面上印刷光环氧树脂层，以标记要切割的划线。 然后沿着光环氧树脂层中的标记通过基板进行蚀刻。 通过典型的美术设计刀将面板切割成单独的包装，该步骤不仅避免了每个模具边缘的粗糙度，而且降低了切割过程的成本。