公开(公告)号：US5867331A

公开(公告)日：1999-02-02

申请号：US843479

申请日：1997-04-16

申请人： Richard T. Behrens ,  Neal Glover

发明人： Richard T. Behrens ,  Neal Glover

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To increase the throughput of the read channel, multiple sample values are processed in parallel. In the example embodiment disclosed herein, two sample values are processed in parallel.

摘要翻译： 公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 为了增加读取通道的吞吐量，并行处理多个采样值。 在本文公开的示例实施例中，并行处理两个采样值。

公开(公告)号：US5812334A

公开(公告)日：1998-09-22

申请号：US210302

申请日：1994-03-16

申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan Armstrong ,  Trent Dudley ,  Bill Foland ,  Neal Glover ,  Larry King

发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan Armstrong ,  Trent Dudley ,  Bill Foland ,  Neal Glover ,  Larry King

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。 公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

公开(公告)号：US5359631A

公开(公告)日：1994-10-25

申请号：US954350

申请日：1992-09-30

申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

IPC分类号： G11B20/10 ,  G11B20/14 ,  H03D13/00 ,  H03L7/00 ,  H03L7/085 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04 ,  H04L7/10 ,  H03D3/24

CPC分类号： G11B20/10037 ,  G11B20/1403 ,  H03D13/005 ,  H03L7/091 ,  H04L7/0334 ,  H04L7/04 ,  H04L7/046 ,  H04L7/10

摘要： A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

摘要翻译： 具有模拟数字转换器以对模拟信号进行采样的定时电路，用于控制模数转换器的采样时间的受控振荡器，用于检测模拟信号中的脉冲的电路，相位误差电路，以从 另一个创建相位误差测量和频率误差电路，将两个样本相加在一起以创建频率误差测量。 两个样本取自脉冲的任一侧。 相位误差测量由受控振荡器用于调整采样定时以在脉冲的所需位置采样。 电路还包含用于补偿不对称脉冲的常数值，并补偿靠近检测到的脉冲发生的其他脉冲。 电路还插入已知频率代替模拟信号以建立受控振荡器的频率。

公开(公告)号：US5844920A

公开(公告)日：1998-12-01

申请号：US745913

申请日：1996-11-07

申请人： Christopher P. Zook ,  Neal Glover ,  Alan J. Armstrong

发明人： Christopher P. Zook ,  Neal Glover ,  Alan J. Armstrong

IPC分类号： G11B5/012 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  G11B20/10

CPC分类号： G11B20/1217 ,  G11B20/1426 ,  G11B20/1813 ,  G11B27/3027 ,  G11B5/012 ,  G11B2020/1476 ,  G11B2220/20

摘要： A magnetic disk storage system is disclosed wherein byte synchronization to sector data is achieved even when noise in the read channel, due for instance to a thermal asperity (TA), corrupts the primary preamble and/or sync mark fields or causes a loss of frequency or phase lock. The data sector format is modified to comprise at least one secondary sync mark in addition to the conventional primary sync mark recorded at the beginning of the data field. In this manner, when the primary sync mark becomes undetectable due to errors, or when byte synchronization is lost, the storage system can still synchronize to the data sector using the secondary sync mark. The secondary sync mark is preferably spaced apart from the primary sync mark with either a gap (no data) or user data inserted inbetween. In the latter embodiment, two methods are employed to recover user data inbetween the primary and secondary sync marks when the primary sync mark is undetectable: on-the-fly erasure pointer error correction, and buffering to facilitate retroactive synchronization. The secondary sync mark may optionally include a secondary preamble to facilitate phase locking to the data when the primary preamble is corrupted by errors. The present invention also provides "split segment" resynchronization for synchronizing a first section of data using a first mark, and retroactively synchronizing a second section of data using a following sync mark when synchronization is lost.

摘要翻译： 公开了一种磁盘存储系统，其中即使由于例如热不平坦（TA）而导致的读通道中的噪声破坏了主前同步码和/或同步标记场，也导致频率损失，实现了与扇区数据的字节同步 或锁相。 修改数据扇区格式，除了在数据字段的开始处记录的常规主同步标记之外还包括至少一个辅助同步标记。 以这种方式，当主同步标记由于错误而变得不可检测，或者当字节同步丢失时，存储系统仍然可以使用辅助同步标记与数据扇区同步。 次同步标记优选地与主同步标记间隔开，间隙（无数据）或插入其间的用户数据。 在后一实施例中，当主同步标记不可检测时，采用两种方法来恢复主同步标记和辅同步标记之间的用户数据：即时擦除指针错误校正和缓冲以便于追溯同步。 辅助同步标记可以可选地包括辅助前同步码，以便在主要前同步码被错误破坏时便于锁定数据。 本发明还提供了用于使用第一标记来同步第一部分数据的“分割段”重新同步，并且当同步丢失时使用后续同步标记追溯地同步第二数据段。

公开(公告)号：US5751733A

公开(公告)日：1998-05-12

申请号：US710293

申请日：1996-09-16

申请人： Neal Glover

发明人： Neal Glover

IPC分类号： G11B20/18

CPC分类号： G11B20/1866

摘要： A disc drive storage system is disclosed that employs sector level and track level error correction systems (ECS), wherein the track level error correction capability is increased by interleaving the track level redundancy. In the preferred embodiment, each sector on the disc is divided into three interleaves or codewords with sector level redundancy generated for each interleaved codeword. The track level redundancy is then generated by combining the interleaved codewords separately according to a predetermined error correction operation (e.g., byte XOR) to form an interleaved redundancy sector. During readback, the sector level ECS generates an erasure pointer corresponding to an uncorrectable codeword within a sector for use by the track level ECS. In this manner, the track level ECS can correct up to three uncorrectable sectors when three sectors contain a single uncorrectable codeword in separate interleaves.

摘要翻译： 公开了一种采用扇区级和磁道级纠错系统（ECS）的磁盘驱动器存储系统，其中通过交织磁道级冗余来提高磁道级纠错能力。 在优选实施例中，盘上的每个扇区被划分成为每个交织的码字产生扇区级冗余的三个交织或码字。 然后通过根据预定的纠错操作（例如，字节XOR）单独组合交织的码字来产生轨道级冗余，以形成交织的冗余扇区。 在回读期间，扇区级ECS生成与扇区内的不可校正码字对应的擦除指针，以由轨道级ECS使用。 以这种方式，当三个扇区在单独的交织中包含单个不可校正的码字时，轨道电平ECS可校正多达三个不可校正扇区。

公开(公告)号：US5473620A

公开(公告)日：1995-12-05

申请号：US124938

申请日：1993-09-21

申请人： Christopher P. Zook ,  Neal Glover

发明人： Christopher P. Zook ,  Neal Glover

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/15

CPC分类号： G06F11/1004 ,  G06F11/10 ,  H03M13/151

摘要： An apparatus and method of generating redundancy symbols and syndromes which is order-programmable is disclosed. The apparatus and method involves the implementation of an error correcting encoder/decoder for polynomial codes which uses a single circuit to generate check symbols during the transmit operation and to generate syndromes during a receive operation. The selection of roots for the code generator, and hence, the code order is programmable.

摘要翻译： 公开了一种生成可编程序列的冗余符号和校正子的装置和方法。 该装置和方法包括实施用于多项式代码的纠错编码器/解码器，其使用单个电路在发送操作期间产生校验符号并且在接收操作期间产生校正符号。 代码生成器的根的选择，因此代码顺序是可编程的。

公开(公告)号：US5280488A

公开(公告)日：1994-01-18

申请号：US612430

申请日：1990-11-08

申请人： Neal Glover ,  Trent Dudley

发明人： Neal Glover ,  Trent Dudley

IPC分类号： G11B20/18 ,  H03M13/15 ,  H03M13/17 ,  G06F11/10

CPC分类号： H03M13/151 ,  G11B20/1833 ,  H03M13/17

摘要： Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.

摘要翻译： 公开了用于提供用于对Reed-Solomon和相关代码进行编码和解码的改进系统的装置和方法。 该系统采用k位串行移位寄存器进行编码和残差生成。 对于解码，在读取数据时产生残差。 单脉冲串错误通过对该残余物进行操作的k位串行突发捕获解码器实时校正。 使用非实时固件解码器校正大于单个突发的错误情况，该解码器检索残差并将其转换为余数，然后将余数转换为综合征，然后尝试计算来自综合征的错误位置和值。 在优选实施例中，在突发捕获电路内采用新的低阶第一，k位串行有限域常数乘法器。 此外，支持不需要等于信息字节大小的代码符号大小。 所公开的方法的实现者可以选择用于多脉冲串校正的时间效率或空间有效的固件。

公开(公告)号：US4562577A

公开(公告)日：1985-12-31

申请号：US533828

申请日：1983-09-19

申请人： Neal Glover ,  Michael J. O'Keeffe ,  S. Robert Perera

发明人： Neal Glover ,  Michael J. O'Keeffe ,  S. Robert Perera

IPC分类号： G11B20/18 ,  H03M13/15 ,  G06F11/10

CPC分类号： G11B20/1833 ,  H03M13/15

摘要： A shared encoder/decoder circuit for use with a Reed-Solomon coding scheme of an optical disk storage system. The optical disk system includes a drive adapted to permanently store data on a removable platter. Prior to recording a data byte on the platter, the data is encoded with a Reed-Solomon code. When the data is read from the disk, it is decoded and error correction syndromes are generated. The same circuitry is shared for performing the encoding and decoding functions. This circuitry includes independent sets of a RAM, coupled to one input of an exclusive OR (modulo two sum) adding circuit. The output of the adding circuit is fed back to an input to the RAM. Two multiplier circuits are coupled to the output of the RAM. A product of one is tied to one input of the modulo two addition circuit. The product of the other is combined with similar products from other sets, and the resulting combination signal is selectively connected to the other input of the modulo two addition circuit, along with data to be recorded on the platter, or data read from the platter.

摘要翻译： 一种用于光盘存储系统的Reed-Solomon编码方案的共享编码器/解码器电路。 光盘系统包括适于将数据永久存储在可移动盘片上的驱动器。 在盘片上记录数据字节之前，用Reed-Solomon码对数据进行编码。 当从磁盘读取数据时，它被解码并产生纠错综合征。 共享相同的电路用于执行编码和解码功能。 该电路包括独立的一组RAM，耦合到异或（模二和）加法电路的一个输入。 加法电路的输出反馈到RAM的输入。 两个乘法器电路耦合到RAM的输出。 一个乘积被连接到模二加法电路的一个输入端。 另一个的产品与来自其他集合的类似产品组合，并且所得到的组合信号被选择性地连接到模二加法电路的另一输入以及要记录在盘片上的数据或从盘片读取的数据。

公开(公告)号：US06125469A

公开(公告)日：2000-09-26

申请号：US137126

申请日：1998-08-20

申请人： Christopher P. Zook ,  Neal Glover ,  John J. Schadegg, Jr.

发明人： Christopher P. Zook ,  Neal Glover ,  John J. Schadegg, Jr.

IPC分类号： G11B20/18

CPC分类号： G11B20/10527 ,  G11B20/1217 ,  G11B20/1833 ,  G11B2020/10759 ,  G11B2020/10787 ,  G11B2020/1287 ,  G11B2020/1843 ,  G11B2220/20

摘要： A magnetic disk storage device employing an on-the-fly, multiple burst error correction system for detecting and correcting errors in data sectors stored on a magnetic disk, wherein each data sector comprises a data field and multiple sync marks for synchronizing to the data field. Multiple sync marks improve the probability of successful byte synchronization to the data field in the presence of noise in the system, such as defects in the storage medium. Further, a sync mark may be embedded within the data field to facilitate byte resynchronization when synchronization is lost.

摘要翻译： 一种磁盘存储装置，其采用运行中的多脉冲串错误校正系统，用于检测和校正存储在磁盘上的数据扇区中的错误，其中每个数据扇区包括用于与数据字段同步的数据字段和多个同步标记 。 多个同步标记提高了在系统中存在噪声（例如存储介质中的缺陷）时与数据字段成功的字节同步的概率。 此外，同步标记可以嵌入在数据字段内，以便在失去同步时便于字节重新同步。

公开(公告)号：US06098192A

公开(公告)日：2000-08-01

申请号：US932121

申请日：1997-09-17

申请人： Neal Glover

发明人： Neal Glover

IPC分类号： G06F7/72 ,  H03M13/15 ,  G11C29/00

CPC分类号： H03M13/158 ,  G06F7/724 ,  H03M13/15

摘要： A cost reduced finite field processor is disclosed for computing the logarithm LOG.sub..alpha. (.alpha..sup.j) of an element of a finite field GF(2.sup.n) using significantly less circuitry than that required by a lookup table typically employed in the prior art. The result of the logarithm (i.e., the exponent of .alpha..sup.j) is represented as a binary number computed serially one bit per clock cycle. In one embodiment, combinatorial logic is used to compute bit 0 of the exponent. On each clock cycle, the exponent is shifted once to the right and bit of the exponent is extracted until the entire exponent has been computed. Shifting the exponent of a field element to the right is carried out by taking the square root of the element. The present invention requires at most n+1 clock cycles to compute LOG.sub..alpha. (.alpha..sup.j), with one embodiment requiring n/2 clock cycles. The circuitry for computing the square root of a field element and for computing bit 0 of the logarithm of a field element is significantly less than that required to implement the logarithm operation using a lookup table.

摘要翻译： 公开了一种成本降低的有限域处理器，用于使用比现有技术中通常采用的查找表所需的电路少得多的电路来计算有限域GF（2n）的元素的对数LOG alpha（alpha j）。 对数的结果（即，αj的指数）被表示为每个时钟周期连续地计算1比特的二进制数。 在一个实施例中，组合逻辑用于计算指数的位0。 在每个时钟周期，指数向右移一次，指数的位被提取，直到计算整个指数。 通过取该元素的平方根来执行向右移动一个字段元素的指数。 本发明最多需要n + 1个时钟周期来计算LOGα（αj），一个实施例需要n / 2个时钟周期。 用于计算场元素的平方根和用于计算场元素的对数的位0的电路显着小于使用查找表来实现对数运算所需的电路。