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    Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures
    22.
    发明申请
    Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures 有权
    在非易失性存储器和非易失性存储器结构中互连导电栅极的导线的制造

    公开(公告)号：US20050199956A1

    公开(公告)日：2005-09-15

    申请号：US10798475

    申请日：2004-03-10

    Applicant: Yi Ding

    Inventor： Yi Ding

    IPC: H01L21/336 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788

    CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

    Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

    Abstract translation: 在非易失性存储器中，选择栅极（144S）由一个导电层（例如多晶硅或多边形）形成，并且互连选择栅极的字线（144）由不同的导电层（例如金属）制成。 字线覆盖在控制栅极（134）上形成的层间电介质（310）。 可以控制电介质厚度以减小字线和控制门之间的电容。 在一些实施例中，使用浮动栅极层的各向同性蚀刻，以自对准的方式制造浮置栅极（120）。

    Floating gate memory structures and fabrication methods
    23.
    发明申请
    Floating gate memory structures and fabrication methods 审中-公开
    浮栅存储器结构和制造方法

    公开(公告)号：US20050196913A1

    公开(公告)日：2005-09-08

    申请号：US11102329

    申请日：2005-04-07

    Applicant: Chia-Shun Hsiao ,  Yi Ding

    Inventor： Chia-Shun Hsiao ,  Yi Ding

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L21/8238

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/66825

    Abstract: Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.

    Abstract translation: 电介质区域（210）形成在非易失性存储单元的有源区域之间的半导体衬底上。 蚀刻电介质区域侧壁的顶部以将顶部部分横向远离有源区域。 然后沉积导电层以形成浮栅（410）。 电介质侧壁的凹陷部分允许浮动栅极在顶部较宽。 结果，门耦合比增大。 还提供其他功能。

    Nonvolatile memory cell with multiple floating gates formed after the select gate
    24.
    发明申请
    Nonvolatile memory cell with multiple floating gates formed after the select gate 有权

    公开(公告)号：US20050174851A1

    公开(公告)日：2005-08-11

    申请号：US11102066

    申请日：2005-04-08

    Applicant: Yi Ding

    Inventor： Yi Ding

    IPC: G11C11/34 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L29/788

    CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

    Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

    Nonvolatile memories with a floating gate having an upward protrusion
    26.
    发明授权
    Nonvolatile memories with a floating gate having an upward protrusion 有权
    具有向上突起的浮动栅极的非易失性存储器

    公开(公告)号：US06893921B2

    公开(公告)日：2005-05-17

    申请号：US10411813

    申请日：2003-04-10

    Applicant: Yi Ding

    Inventor： Yi Ding

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L27/108

    CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L29/42324

    Abstract: In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

    Abstract translation: 在非易失性存储单元中，浮动栅极（160）具有向上突出部分。 该部分可以形成为在选择门（140）的侧壁上的间隔物。 隔离物可以由沉积在提供浮动栅极的下部的层（160.1）之后的层（160.2）形成。 或者，向上突出部分和下部分可以由相同的层或子层形成，所有这些层或子层都存在于两个部分中。 控制栅极（170）可以在没有光刻的情况下被定义。 还提供了其他实施例。

    System and method for charging a battery
    27.
    发明申请
    System and method for charging a battery 失效
    电池充电的系统和方法

    公开(公告)号：US20050099162A1

    公开(公告)日：2005-05-12

    申请号：US10702813

    申请日：2003-11-06

    Applicant: Yi Ding

    Inventor： Yi Ding

    IPC: H02J7/00 ,  H02J7/04

    CPC classification number: H02J7/0093

    Abstract: A system and method for charging a battery is provided. The method includes applying an excitation current pulse to the battery to determine the battery type and whether the battery is capable of holding a charge. To charge the battery, a series of current pulses are applied in groups with the average current being reduced for each succeeding group to take advantage of changing battery charge acceptance. When the voltage of the battery matches a predetermined value, application of the current pulse groups is ended. A single current pulse is then applied to complete the battery charge.

    Abstract translation: 提供一种用于对电池充电的系统和方法。 该方法包括向电池施加激励电流脉冲以确定电池类型以及电池是否能够保持电荷。 为了对电池充电，对于每个后续组，一组电流脉冲以平均电流减小的方式被组合，以利用改变电池充电的接受程度。 当电池的电压匹配预定值时，结束当前脉冲组的施加。 然后施加单个电流脉冲来完成电池充电。

    Detector for rapid charging and method
    29.
    发明授权
    Detector for rapid charging and method 有权
    快速充电检测仪及方法

    公开(公告)号：US06229285B1

    公开(公告)日：2001-05-08

    申请号：US09543275

    申请日：2000-04-05

    Applicant: Yi Ding

    Inventor： Yi Ding

    IPC: H02J700

    CPC classification number: H02J7/0008 ,  H01M10/44 ,  H02J7/0093 ,  Y02B40/90

    Abstract: Detectors and methods for rapid charging each provide efficient recharging of batteries of various types and ratings. During the charging process, the detector preferably monitors battery state of charge (SOC) and/or battery charge acceptance (BCA) in order to select appropriate waveforms for the charging signal. The charging signal may be a pulse width and amplitude modulated current, voltage or power waveform with the amplitude and pulse width of each charging pulse being selected based upon the detected battery SOC and/or BCA.

    Abstract translation: 用于快速充电的探测器和方法为每种类型和等级的电池提供有效的充电。 在充电过程中，检测器优选地监视电池充电状态（SOC）和/或电池充电接受（BCA），以便为充电信号选择合适的波形。 充电信号可以是基于检测到的电池SOC和/或BCA来选择每个充电脉冲的幅度和脉冲宽度的脉冲宽度和幅度调制电流，电压或功率波形。

    System and method for battery charging with acoustic excitation
    30.
    发明授权
    System and method for battery charging with acoustic excitation 失效
    带有声激发电池充电的系统和方法

    公开(公告)号：US5932991A

    公开(公告)日：1999-08-03

    申请号：US014388

    申请日：1998-01-28

    Applicant: Krisham K. Ahuja ,  Yi Ding

    Inventor： Krisham K. Ahuja ,  Yi Ding

    IPC: H01M10/42 ,  H01M10/44 ,  H02J7/00

    CPC classification number: H02J7/0073 ,  H01M10/4214 ,  H01M10/44 ,  H02J7/0093

    Abstract: The present invention is a system and method for enhancing the charging of a battery by exposing the battery to acoustic excitation while the battery is being charged. By adding acoustic excitation to the charging process, the present invention reduces the time needed to charge the battery, reduces the energy needed for charging, and increases the battery's cycle life. The present invention may be used to charge new and used batteries and to rejuvenate dead batteries.

    Abstract translation: 本发明是一种通过在电池充电时将电池暴露于声学激发来增强电池的充电的系统和方法。 通过在充电过程中增加声学激发，本发明减少了对电池充电所需的时间，减少了充电所需的能量，并且增加了电池的循环寿命。 本发明可以用于对新的和使用过的电池充电并且使死电池复原。

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