公开(公告)号：US20110216588A1

公开(公告)日：2011-09-08

申请号：US13039004

申请日：2011-03-02

申请人： Yong June Kim ,  Jaehong Kim ,  Junjin Kong ,  Hong Rak Son

发明人： Yong June Kim ,  Jaehong Kim ,  Junjin Kong ,  Hong Rak Son

IPC分类号： G11C16/04

CPC分类号： G11C16/04

摘要： A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits.

摘要翻译： 存储器件包括多个多位存储器单元。 根据纠错码对多个输入数据位进行编码，以产生包括多个位组的码字。 多个多位存储器单元中的相应的多位存储器单元被编程为表示码字的位组中的相应的一组。 码字的比特组可以是连续比特的组。 在一些实施例中，多位存储器单元被配置为以比特存储，并且码字的长度是m的整数倍。 可以从页单元或单元单元中的多位存储单元读取数据以恢复码字，并且可以根据纠错码对恢复的码字进行解码以恢复输入数据位。

公开(公告)号：US20100202198A1

公开(公告)日：2010-08-12

申请号：US12654578

申请日：2009-12-23

申请人： Yong June Kim ,  Junjin Kong ,  Jaehong Kim ,  Hong Rak Son

发明人： Yong June Kim ,  Junjin Kong ,  Jaehong Kim ,  Hong Rak Son

IPC分类号： G11C16/04

CPC分类号： G11C13/00 ,  G11C7/1006 ,  G11C11/5628 ,  G11C13/0033 ,  G11C16/3427 ,  G11C29/00

摘要： Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.

摘要翻译： 提供了一种半导体存储器件中的数据处理方法。 数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。 数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

公开(公告)号：US20100077279A1

公开(公告)日：2010-03-25

申请号：US12507096

申请日：2009-07-22

申请人： Yong June Kim ,  Jaehong Kim ,  Junjin Kong

发明人： Yong June Kim ,  Jaehong Kim ,  Junjin Kong

IPC分类号： H04L1/00 ,  G06F11/08

CPC分类号： H03M13/373 ,  G06F11/1068 ,  H03M13/13 ,  H03M13/455

摘要： Provided are data processing methods for a non-volatile memory. The data processing methods include obtaining read data and erasure information from the non-volatile memory and correcting an error in the read data by referencing the erasure information obtained from the non-volatile memory. Memory systems may be provided. Such memory systems may include a non-volatile memory and a memory controller that is operable to perform an error correction operation according to the methods described herein.

摘要翻译： 提供了用于非易失性存储器的数据处理方法。 数据处理方法包括从非易失性存储器获取读取数据和擦除信息，并通过参考从非易失性存储器获取的擦除信息来校正读取数据中的错误。 可以提供存储器系统。 这样的存储器系统可以包括非易失性存储器和可操作以根据本文所述的方法执行纠错操作的存储器控​​制器。

公开(公告)号：US08583855B2

公开(公告)日：2013-11-12

申请号：US12780979

申请日：2010-05-17

申请人： Han-woong Yoo ,  Jaehong Kim ,  Jun-jin Kong

发明人： Han-woong Yoo ,  Jaehong Kim ,  Jun-jin Kong

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7209

摘要： A flash memory preprocessing system comprises at least one flash memory device, a memory controller controlling program and read operations of the at least one flash memory device, and a flash preprocessor receiving program data from an external source, generating preprocessed data by converting the received program data, and outputting the preprocessed data to the memory controller. The memory controller controls the at least one flash memory device to perform a program operation on the at least one flash memory device according to the preprocessed data.

摘要翻译： 闪存预处理系统包括至少一个闪存器件，存储器控制器控制程序和至少一个闪速存储器件的读取操作，以及从外部源接收程序数据的闪速预处理器，通过转换所接收的程序来产生预处理数据 数据，并将预处理的数据输出到存储器控制器。 所述存储器控制器控制所述至少一个闪速存储器件，以根据所述预处理数据对所述至少一个闪存器件执行编程操作。

公开(公告)号：US08441862B2

公开(公告)日：2013-05-14

申请号：US13080809

申请日：2011-04-06

申请人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

发明人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.

摘要翻译： 提供了具有排列成行和列的存储单元的多位存储器件的编程方法。 程序方法包括根据第一级别的第一组验证电压电平的验证电压电平将第一组存储器单元的每个存储器单元编程到第一组状态内的状态，以及编程每个存储器 第二组存储器单元的单元根据在第二级别范围内的第二组验证电压电平的验证电压电平而处于第二组状态内的状态。 第二级别的最低验证电压电平高于第一级别范围内的最高验证电压电平。 在第一级别范围内的相邻验证电压电平之间的第一电压差不同于第二组验证电压电平的最高验证电压电平与第三组验证电压电平的最低验证电压电平之间的第二电压差 。

公开(公告)号：US20110249496A1

公开(公告)日：2011-10-13

申请号：US13080809

申请日：2011-04-06

申请人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

发明人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.

摘要翻译： 提供了具有排列成行和列的存储单元的多位存储器件的编程方法。 程序方法包括根据第一级别的第一组验证电压电平的验证电压电平将第一组存储器单元的每个存储器单元编程到第一组状态内的状态，以及编程每个存储器 第二组存储器单元的单元根据在第二级别范围内的第二组验证电压电平的验证电压电平而处于第二组状态内的状态。 第二级别的最低验证电压电平高于第一级别范围内的最高验证电压电平。 在第一级别范围内的相邻验证电压电平之间的第一电压差不同于第二组验证电压电平的最高验证电压电平与第三组验证电压电平的最低验证电压电平之间的第二电压差 。

公开(公告)号：US08812942B2

公开(公告)日：2014-08-19

申请号：US12944807

申请日：2010-11-12

申请人： Jaehong Kim ,  Hee-Seok Eun ,  Ki-Jun Lee ,  Yong-June Kim

发明人： Jaehong Kim ,  Hee-Seok Eun ,  Ki-Jun Lee ,  Yong-June Kim

IPC分类号： G06F11/00

CPC分类号： G06F12/0607 ,  G06F2212/7208

摘要： An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

摘要翻译： 交错装置可以包括：第一缓冲器单元，被配置为以具有扇区大小的单位缓冲输入数据以产生扇区单元数据;编码单元，被配置为对扇区单元数据进行编码，并且基于编码生成多个奇偶校验码， 第二缓冲器单元，被配置为交织扇区单元数据和奇偶校验码，并且基于交织产生交织数据，第二缓冲单元包括被配置为存储交织数据的多个输出缓冲器，以及输出单元，其被配置为输出交织 数据。

公开(公告)号：US08587997B2

公开(公告)日：2013-11-19

申请号：US13016063

申请日：2011-01-28

申请人： Jaehong Kim ,  Kijun Lee ,  Yong June Kim ,  Heeseok Eun

发明人： Jaehong Kim ,  Kijun Lee ,  Yong June Kim ,  Heeseok Eun

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/26

摘要： Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols.

摘要翻译： 提供了一种存储器系统及其操作方法。 操作方法用不同的读取电压至少一次读取观察存储器单元以配置第一读取数据符号，至少用不同的读取电压读取与观察存储器单元相邻的多个干扰存储器单元以配置第二读取数据 符号，并且基于第一读取数据符号和第二读取数据符号确定观察存储器单元的逻辑值。

公开(公告)号：US20100115377A1

公开(公告)日：2010-05-06

申请号：US12607768

申请日：2009-10-28

申请人： Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

发明人： Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1108 ,  G06F11/1072

摘要： A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.

摘要翻译： 至少由纠错码（ECC）解码器和控制器实施的方法估计和校正存储器单元中的错误。 该方法包括使用第一种误差估计方法来识别具有错误产生可能性的存储器单元的第一候选组; 使用用于错误估计的第二方法识别具有错误生成可能性的第二候选组存储器单元; 以及校正通常包括在第一和第二候选组中的至少一个单元中的错误。

公开(公告)号：US08891300B2

公开(公告)日：2014-11-18

申请号：US13746640

申请日：2013-01-22

申请人： Eun Chu Oh ,  Jaehong Kim ,  Jongha Kim ,  Junjin Kong

发明人： Eun Chu Oh ,  Jaehong Kim ,  Jongha Kim ,  Junjin Kong

IPC分类号： G11C16/04 ,  G06F12/02 ,  G11C11/56 ,  G11C16/10 ,  H01L27/115

CPC分类号： G06F12/0246 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5646 ,  H01L27/11582

摘要： In one embodiment, the method includes overwriting a memory cell storing m-bit data to store n-bit data, where n is less than or equal to m. The memory cell has one of a first plurality of program states when storing the m-bit data, and the memory cell has one of a second plurality of program states when storing the n-bit data. The second plurality of program states include at least one program state not in the first plurality of program states.

摘要翻译： 在一个实施例中，该方法包括重写存储m位数据以存储n位数据的存储单元，其中n小于或等于m。 当存储m位数据时，存储单元具有第一多个程序状态之一，并且当存储n位数据时存储单元具有第二多个程序状态之一。 第二多个程序状态包括不在第一多个程序状态中的至少一个程序状态。