公开(公告)号：US07638387B2

公开(公告)日：2009-12-29

申请号：US11823381

申请日：2007-06-27

Applicant: Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

Inventor： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

IPC: H01L21/8234

CPC classification number: H01L27/1021

Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

Abstract translation: 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

公开(公告)号：US20090065850A1

公开(公告)日：2009-03-12

申请号：US12266201

申请日：2008-11-06

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L29/792

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78645

Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Abstract translation: 根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。 因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。

公开(公告)号：US07402493B2

公开(公告)日：2008-07-22

申请号：US11602032

申请日：2006-11-20

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L21/336

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78645

Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Abstract translation: 根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。 因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。

公开(公告)号：US06784476B2

公开(公告)日：2004-08-31

申请号：US10039126

申请日：2002-01-03

Applicant: Dong-Jun Kim ,  Jin-Ho Kim ,  Yong-Kyu Lee ,  Min-Soo Cho ,  Eui-Youl Ryu

Inventor： Dong-Jun Kim ,  Jin-Ho Kim ,  Yong-Kyu Lee ,  Min-Soo Cho ,  Eui-Youl Ryu

IPC: H01L27108

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42328

Abstract: In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.

Abstract translation: 在非易失性半导体存储器件及其制造方法中，在基板上形成电荷存储层。 在电荷存储层上形成控制栅极层。 在控制栅极层上形成具有间隔物形状的栅极掩模。 使用栅极掩模去除电荷存储层和控制栅极层作为保护以形成控制栅极和电荷存储区域。

公开(公告)号：US06724661B2

公开(公告)日：2004-04-20

申请号：US10090902

申请日：2002-05-31

Applicant: Yong-Kyu Lee ,  Dong-Jun Kim ,  Min-Soo Cho ,  Eui-Youl Ryu ,  Jin-Ho Kim

Inventor： Yong-Kyu Lee ,  Dong-Jun Kim ,  Min-Soo Cho ,  Eui-Youl Ryu ,  Jin-Ho Kim

IPC: G11C1604

CPC classification number: G11C16/14

Abstract: A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.

Abstract translation: 一种在存储单元中执行擦除操作的方法。 分别在源极和漏极区域施加第一电压和第二电压达预定的擦除时间; 并且第一和第二电压在源极和漏极区之间彼此切换至少一次以用于擦除时间。 因此，孔容易地注入到源极和漏极区域以及沟道横向表面，并且存储均匀且高速的擦除操作。

公开(公告)号：US09330745B2

公开(公告)日：2016-05-03

申请号：US14509756

申请日：2014-10-08

Applicant: Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

Inventor： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Abstract translation: 磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。 第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。 固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。 磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。 还讨论了相关的操作方法。

公开(公告)号：US09208874B2

公开(公告)日：2015-12-08

申请号：US14083470

申请日：2013-11-19

Applicant: Yong-Kyu Lee ,  Bo-Geun Kim

Inventor： Yong-Kyu Lee ,  Bo-Geun Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0085 ,  G11C2211/5622 ,  G11C2213/72

Abstract: A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.

Abstract translation: 提供了用于驱动非易失性存储器件的方法。 该方法包括基于预定电流选择第一写入驱动器，对与第一写入驱动器相对应的电阻存储器单元执行第一编程操作，在第一程序操作中验证电阻性存储器单元是否已经通过或失败，以及关于故障位的排序信息 在第一程序操作中失败的存储器单元，基于分类的故障位存储器单元信息选择第二写驱动器，以及对与第二写驱动器相对应的电阻存储单元执行第二程序操作。

公开(公告)号：US08921816B2

公开(公告)日：2014-12-30

申请号：US13178762

申请日：2011-07-08

Applicant: Bo-Young Seo ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

Inventor： Bo-Young Seo ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

IPC: H01L29/02 ,  H01L27/24 ,  H01L27/102 ,  H01L45/00

CPC classification number: H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Abstract translation: 提供一种半导体器件。 该半导体器件包括半导体衬底上的下部有源区。 提供从下部有源区域的顶表面突出并且具有比下部有源区域更窄的多个上部有源区域。 提供了围绕下部有源区域的侧壁的下部隔离区域。 提供了形成在下隔离区域上的上隔离区域，其围绕上活性区域的侧壁，并且具有比下隔离区域窄的宽度。 提供形成在下部有源区并延伸到上部有源区的第一杂质区。 提供形成在上部有源区并与第一杂质区一起构成二极管的第二杂质区。 还提供了制造该方法的方法。

公开(公告)号：US20120007212A1

公开(公告)日：2012-01-12

申请号：US13178762

申请日：2011-07-08

Applicant: Bo-Young SEO ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

Inventor： Bo-Young SEO ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

IPC: H01L29/06

CPC classification number: H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Abstract translation: 提供一种半导体器件。 该半导体器件包括半导体衬底上的下部有源区。 提供从下部有源区域的顶表面突出并且具有比下部有源区域更窄的多个上部有源区域。 提供了围绕下部有源区域的侧壁的下部隔离区域。 提供了形成在下隔离区域上的上隔离区域，其围绕上活性区域的侧壁，并且具有比下隔离区域窄的宽度。 提供形成在下部有源区并延伸到上部有源区的第一杂质区。 提供形成在上部有源区并与第一杂质区一起构成二极管的第二杂质区。 还提供了制造该方法的方法。

公开(公告)号：US07745871B2

公开(公告)日：2010-06-29

申请号：US11871453

申请日：2007-10-12

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L29/78

CPC classification number: H01L29/7854 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78645

Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。