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    Semiconductor device having a diode
    1.
    发明授权
    Semiconductor device having a diode 有权
    具有二极管的半导体器件

    公开(公告)号：US08921816B2

    公开(公告)日：2014-12-30

    申请号：US13178762

    申请日：2011-07-08

    申请人： Bo-Young Seo ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

    发明人： Bo-Young Seo ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

    IPC分类号： H01L29/02 ,  H01L27/24 ,  H01L27/102 ,  H01L45/00

    CPC分类号： H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06

    摘要： Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

    摘要翻译： 提供一种半导体器件。 该半导体器件包括半导体衬底上的下部有源区。 提供从下部有源区域的顶表面突出并且具有比下部有源区域更窄的多个上部有源区域。 提供了围绕下部有源区域的侧壁的下部隔离区域。 提供了形成在下隔离区域上的上隔离区域，其围绕上活性区域的侧壁，并且具有比下隔离区域窄的宽度。 提供形成在下部有源区并延伸到上部有源区的第一杂质区。 提供形成在上部有源区并与第一杂质区一起构成二极管的第二杂质区。 还提供了制造该方法的方法。

    Non-volatile memory device
    2.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08526231B2

    公开(公告)日：2013-09-03

    申请号：US13177873

    申请日：2011-07-07

    申请人： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    发明人： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

    摘要： A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

    摘要翻译： 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

    Semiconductor device and method of fabricating semiconductor device
    4.
    发明授权
    Semiconductor device and method of fabricating semiconductor device 有权
    半导体器件及半导体器件的制造方法

    公开(公告)号：US08476130B2

    公开(公告)日：2013-07-02

    申请号：US13180613

    申请日：2011-07-12

    申请人： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

    发明人： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/2436 ,  H01L27/105 ,  H01L27/2445 ,  H01L45/1683

    摘要： A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.

    摘要翻译： 一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

    Non-Volatile Memory Device
    5.
    发明申请
    Non-Volatile Memory Device 有权
    非易失性存储器件

    公开(公告)号：US20120087189A1

    公开(公告)日：2012-04-12

    申请号：US13177873

    申请日：2011-07-07

    申请人： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    发明人： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

    摘要： A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

    摘要翻译： 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

    EEPROM device and manufacturing method thereof
    8.
    发明申请
    EEPROM device and manufacturing method thereof 失效
    EEPROM装置及其制造方法

    公开(公告)号：US20060006452A1

    公开(公告)日：2006-01-12

    申请号：US11087127

    申请日：2005-03-23

    申请人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    发明人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

    摘要翻译： 提供了一种EEPROM器件及其制造方法。 EEPROM装置由包括存储晶体管和位于半导体衬底上的串联选择晶体管的一个单元组成，并且包括位于存储晶体管的侧面区域上的源极区域，位于选择区域的一个侧面区域的漏极区域 面对源极区域的晶体管，以及形成在存储晶体管和选择晶体管之间的浮置结区，其中浮置结区域包括在存储晶体管占据的区域下朝向源极区域延伸的第一掺杂区域和掺杂 其具有与第一掺杂区域相对的导电掺杂剂并且形成为围绕第一掺杂区域。

    Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same
    9.
    发明申请
    Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same 有权
    减少程序干扰的非易失性半导体存储器件及其编程方法

    公开(公告)号：US20100265765A1

    公开(公告)日：2010-10-21

    申请号：US12662431

    申请日：2010-04-16

    申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

    发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

    IPC分类号： G11C16/02 ,  G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/0433 ,  G11C16/24

    摘要： A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

    摘要翻译： 提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。 连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平 在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。 因此，可以抑制由FN隧穿和结热电子引起的程序干扰。

    EEPROM device having first and second doped regions that increase an effective channel length
    10.
    发明授权
    EEPROM device having first and second doped regions that increase an effective channel length 失效
    具有增加有效沟道长度的第一和第二掺杂区的EEPROM器件

    公开(公告)号：US07408230B2

    公开(公告)日：2008-08-05

    申请号：US11087127

    申请日：2005-03-23

    申请人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    发明人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

    摘要翻译： 提供了一种EEPROM器件及其制造方法。 EEPROM装置由包括存储晶体管和位于半导体衬底上的串联选择晶体管的一个单元组成，并且包括位于存储晶体管的侧面区域上的源极区域，位于选择区域的一个侧面区域的漏极区域 面对源极区域的晶体管，以及形成在存储晶体管和选择晶体管之间的浮置结区，其中浮置结区域包括在存储晶体管占据的区域下朝向源极区域延伸的第一掺杂区域和掺杂 其具有与第一掺杂区域相对的导电掺杂剂并且形成为围绕第一掺杂区域。