公开(公告)号：US5872471A

公开(公告)日：1999-02-16

申请号：US773307

申请日：1996-12-24

申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Akira Yamagiwa ,  Toshitsugu Takekuma ,  Toshiro Takahashi ,  Tatsuhiro Aida

发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Akira Yamagiwa ,  Toshitsugu Takekuma ,  Toshiro Takahashi ,  Tatsuhiro Aida

IPC分类号： H03K19/0185 ,  H04L5/14 ,  H03K17/00

CPC分类号： H03K19/018592 ,  H04L5/1423

摘要： In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal. The receiver has a reference circuit for receiving the logical signal and outputting it to a bias circuit, a bias circuit for generating a divided voltage signal in conjunction with internal resistance of the reference circuit, and a differential receiver for receiving the mixed signal and the divided voltage signal and outputting the difference between them. The reference circuit and the bias circuit are formed by using MOS transistors.

摘要翻译： 在用于经由传输线在LSI之间进行同时双向通信的同时双向传输电路中，连接到传输线的输入/输出电路被包括在LSI中。 输入/输出电路具有驱动器和接收器。 驱动器根据LSI内的逻辑信号将输出信号发送到传输线。 接收机通过传输线接收具有接收信号和输出信号的混合的混合信号。 由LSI中的接收机接收到的信号已被另一方发送到传输线，即与其通信的另一个LSI。 接收器也接收逻辑信号输出。 接收导出混合信号和逻辑信号输出之间的差异，从而从混合信号中去除逻辑信号的分量，并输出接收信号。 接收器具有用于接收逻辑信号并将其输出到偏置电路的参考电路，用于产生与参考电路的内部电阻相分离的电压信号的偏置电路，以及用于接收混合信号和分频的差分接收器 电压信号并输出​​它们之间的差异。 参考电路和偏置电路通过使用MOS晶体管形成。

公开(公告)号：US5794020A

公开(公告)日：1998-08-11

申请号：US663982

申请日：1996-06-14

申请人： Akira Tanaka ,  Toshio Doi ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

发明人： Akira Tanaka ,  Toshio Doi ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

IPC分类号： H04L7/00 ,  G06F1/12 ,  H04L7/02 ,  H04L7/033 ,  H04L7/08

CPC分类号： H04L7/0337 ,  H04L7/0008 ,  H04L7/0041

摘要： A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin. In a normal operation, the judging circuit detects a deviation from the optimum point and the delay amount of the first variable delay circuit is finely adjusted in accordance with the detection, thereby maintaining the latch timing of the reception data at the optimum point.

摘要翻译： 第一可变延迟电路延迟从输入缓冲器输出的发送单元的接收数据，并将延迟的数据生成到数据未识别时间检测部分。 第一和第二锁存器分别在第三锁存器的锁存定时之前和之后以规则的间隔分别具有第二和第三可变延迟电路接收和输出的锁存定时。 在调整操作中，第二和第三可变延迟电路的延迟量被固定为足够小于传送周期的值，可变延迟电路的延迟量增加，判断电路检测到接收的前一边缘 数据，随后，第二和第三可变延迟电路的延迟量依次增加同时保持相同的值，并且检测接收数据的后沿。 在这种情况下，第三锁存器的定时被设置为最大裕量的最佳点。 在正常操作中，判断电路检测到与最佳点的偏差，并且根据检测精细地调整第一可变延迟电路的延迟量，从而将接收数据的锁存定时保持在最佳点。

公开(公告)号：US4329597A

公开(公告)日：1982-05-11

申请号：US81894

申请日：1979-10-04

申请人： Akira Yamagiwa

发明人： Akira Yamagiwa

IPC分类号： H03K19/00 ,  H03K19/086 ,  H03K19/12 ,  H01L31/00

CPC分类号： H03K19/086

摘要： In a logic circuit comprising a low-amplitude CML circuit including a transistor functioning as a constant-current source, the constant-current source transistor is biased by a bias power source which is capable of compensating for both the power supply voltage dependency and the junction temperature dependency of the CML circuit. In the logic circuit, negative feedback is applied to the constant-current source transistor through its base bias circuit to compensate for the dependency of the constant-current source transistor on the power supply voltage, and the difference between the junction temperature dependency of the junction voltage of one of two transistors in the control circuit and that of the other transistor due to the different emitter current densities is utilized to compensate for the dependency of the constant current source transistor on the junction temperature.

摘要翻译： 在包括用作恒流源的晶体管的低振幅CML电路的逻辑电路中，恒流源晶体管被偏置电源偏置，该偏置电源能够补偿电源电压依赖性和结 CML电路的温度依赖性。 在逻辑电路中，负反馈通过其基极偏置电路施加到恒流源晶体管，以补偿恒流源晶体管对电源电压的依赖性，以及结点的结温依赖性之间的差异 利用控制电路中的两个晶体管中的一个的电压和由于不同的发射极电流密度引起的另一晶体管的电压的电压来补偿恒流源晶体管对结温的依赖性。

公开(公告)号：US20070018683A1

公开(公告)日：2007-01-25

申请号：US11523558

申请日：2006-09-20

申请人： Toshitsuqu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsuqu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： H03K19/003

CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

公开(公告)号：US20050127940A1

公开(公告)日：2005-06-16

申请号：US11049663

申请日：2005-02-04

申请人： Toshitsuqu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsuqu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G11C11/401 ,  H03K19/0175 ,  H04B3/02 ,  H04L25/02 ,  H05K1/02 ,  H05K1/14 ,  H03K19/003

CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

摘要翻译： 信号发送电路包括具有用于发送来自驱动电路的信号的驱动电路和块内传输线路的电路块，具有接收电路的电路块和用于将信号发送到所述接收电路的块内传输线路 以及用于在驱动和接收电路块之间传播信号的主块间传输线。 块间​​传输线由具有与块间传输线基本上相同阻抗的电阻端接。 块内传输线路设置有电阻元件，其电阻基本上等于通过将块间传输线路的阻抗的一半从块内传输线路的阻抗减去一半到更低的信号幅度， 抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。

公开(公告)号：US06768346B2

公开(公告)日：2004-07-27

申请号：US10400685

申请日：2003-03-28

申请人： Toshitsugu Takekuma ,  Akira Yamagiwa ,  Takashi Moriyama ,  Ryoichi Kurihara

发明人： Toshitsugu Takekuma ,  Akira Yamagiwa ,  Takashi Moriyama ,  Ryoichi Kurihara

IPC分类号： H03K1906

CPC分类号： G06F13/4077

摘要： A signal transmission system includes a first circuit block having a first output circuit for producing a first signal, a plurality of second circuit blocks each including a first receiving circuit for receiving the first signal, and transmission lines connected between the first circuit block and the second circuit blocks, wherein the first circuit block further includes a second output circuit for producing a second signal, and wherein each of the second circuit blocks further includes a second receiving circuit for receiving the second signal, the first receiving circuit latching the first signal in synchronism with the second signal, removing the unsuccessfulness in the signal transmission and reception due to the propagation delay of signals between circuits.

摘要翻译： 信号传输系统包括：第一电路块，具有用于产生第一信号的第一输出电路;多个第二电路块，每个第二电路块包括用于接收第一信号的第一接收电路;以及连接在第一电路块和第二电路块之间的传输线 电路块，其中所述第一电路块还包括用于产生第二信号的第二输出电路，并且其中每个所述第二电路块还包括用于接收所述第二信号的第二接收电路，所述第一接收电路同步地锁存所述第一信号 利用第二信号，消除由于电路之间的信号的传播延迟引起的信号发送和接收中的不成功。

公开(公告)号：US06441639B1

公开(公告)日：2002-08-27

申请号：US09716251

申请日：2000-11-21

申请人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

发明人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

IPC分类号： H03K1716

CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

摘要： A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission lien itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

摘要翻译： 信号发送电路包括一个或多个具有驱动电路和块内传输线的电路块，用于发送由驱动电路产生的信号，一个或多个电路块具有接收电路和块内传输线，用于发送 信号到所述接收电路，以及主块间传输线，用于在两个驱动和接收电路块之间传播信号。 块间​​传输线在一端或两端由一个或两个具有与块间传输留置本身具有基本相同阻抗的电阻终止。 块内传输线路中的每一个被提供有电阻元件，其电阻等于或接近于通过从块内传输线路的阻抗减去块间传输线路的阻抗的一半导出的值， 降低信号幅度并抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。

公开(公告)号：US06049221A

公开(公告)日：2000-04-11

申请号：US111804

申请日：1998-07-08

申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  H03K19/175

CPC分类号： H03K19/0005

摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

摘要翻译： 具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。 当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。 如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。 当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值 并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。

公开(公告)号：US06034878A

公开(公告)日：2000-03-07

申请号：US992210

申请日：1997-12-16

申请人： Hideki Osaka ,  Masaya Umemura ,  Akira Yamagiwa ,  Toshitsugu Takekuma

发明人： Hideki Osaka ,  Masaya Umemura ,  Akira Yamagiwa ,  Toshitsugu Takekuma

IPC分类号： G06F12/06 ,  G06F1/10 ,  G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C11/401 ,  G11C11/407 ,  G11C13/00

CPC分类号： G06F13/1684

摘要： A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

摘要翻译： 源时钟同步的存储器系统，每个存储体具有大的数据存储容量和高的安装密度。 本发明包括具有通过第一连接器C1安装在基板上的第一存储器提升板B1和通过第二连接器C2安装在基板BB上的第二存储器提升板B2的存储单元。 第一存储器提升板具有安装在其前表面上的多个第一存储器模块，并且第二存储器提升板具有安装在其前表面上的多个第二存储器模块。 第一和第二存储器提升板被布置成使得第一存储器提升板的后表面面向第二存储器提升板的后表面。 本发明还包括板连接连接器，用于将第一存储器提升板上的信号线连接到第二存储器提升板上的相应信号线。

公开(公告)号：US5867541A

公开(公告)日：1999-02-02

申请号：US441613

申请日：1995-05-15

申请人： Akira Tanaka ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

发明人： Akira Tanaka ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

IPC分类号： G06F13/42 ,  H04L7/00 ,  H04L7/033

CPC分类号： H04L7/0337 ,  H04L7/0037 ,  H04L7/0008

摘要： Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.

摘要翻译： 数据从多个发射机中的任何一个与第一时钟同步发送。 接收机与第一时钟同步地接收数据，第二时钟与第一时钟具有预定的相位关系。 先前在接收机中保持与多个发射机有关的数据接收条件的控制信息，以根据控制信息来控制接收机的接收条件。