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公开(公告)号：US4817056A
公开(公告)日：1989-03-28
申请号：US077622
申请日：1987-07-24
IPC分类号： G11C11/401 , G11C11/408 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/84
摘要： In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. The comparator comprises a dynamic NOR gate having discharge paths each formed of a gate element receiving a bit or its inversion of the input address to be opened or closed depending on the value of the particular bit of the input address currently applied, and a PROM element in series with the gate element. The dynamic NOR gate has a first node forming an output thereof and a second node, each of the series connections of the PROM element and the gate element is connected across the first and the second nodes. The potential on the second node is caused to be identical with the potential on the first node during the precharge period.
摘要翻译： 在具有主存储单元的行（行或列）和响应于缺陷行的地址而替代缺陷行的备用存储单元的行的冗余配置的半导体存储器件中，比较器将输入到 存储器件，其中已经编程的缺陷线的地址，并且当发现输入地址与编程地址一致时，备用线选择器选择备用线。 该比较器包括一个动态或非门，每个放电路径均由栅极元件形成，栅极元件根据当前施加的输入地址的特定位的值接收要打开或关闭的输入地址的位或其反相，以及PROM元件 与门元件串联。 动态NOR门具有形成其输出的第一节点和第二节点，PROM元件和门元件的每个串联连接跨越第一节点和第二节点连接。 在预充电期间，使第二节点上的电位与第一节点上的电位相同。
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公开(公告)号：US4797001A
公开(公告)日：1989-01-10
申请号：US79147
申请日：1987-07-29
IPC分类号： G11C11/407 , G11C11/4074 , G11C7/00 , G11C7/02 , H01L27/02 , H03K3/353
CPC分类号： G11C11/4074
摘要： The invention relates to a substrate bias generator for use in dynamic random access memory, and in which either a plurality of transistors for rectification are disposed between a coupling capacitor and a substrate potential electrode or a threshold voltage of a transistor for rectification between the coupling capacitor and the substrate potential electrode is different from a threshold voltage of the other transistor making the absolute value of substrate potential smaller thereby, so that a depletion-layer distance formed between a P-type substrate and N.sup.+ -type substrate is shortened and that effect due to incidence of .alpha.-particle is reduced resulting in reducing soft error rate.
摘要翻译： 本发明涉及一种用于动态随机存取存储器中的衬底偏置发生器，其中用于整流的多个晶体管设置在耦合电容器和衬底电位电极之间，或用于在耦合电容器之间进行整流的晶体管的阈值电压 并且衬底电位电极与另一晶体管的阈值电压不同，使得衬底电位的绝对值变小，使得在P型衬底和N +型衬底之间形成的耗尽层距离缩短，并且由此产生的效应 α粒子发生率降低导致软错误率降低。
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公开(公告)号：US5588130A
公开(公告)日：1996-12-24
申请号：US283367
申请日：1994-08-01
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
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公开(公告)号：US5371714A
公开(公告)日：1994-12-06
申请号：US26225
申请日：1993-02-26
CPC分类号： G11C8/14 , G11C7/1036 , G11C7/1039 , G11C8/18 , H01L2924/01074
摘要： In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.
摘要翻译： 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。
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公开(公告)号：US5103426A
公开(公告)日：1992-04-07
申请号：US528511
申请日：1990-05-25
IPC分类号： H01L21/82 , G11C5/06 , G11C8/00 , G11C8/12 , G11C11/401 , G11C29/00 , H01L21/822 , H01L27/04 , H01L27/10 , H03M7/00 , H03M7/22
CPC分类号： G11C8/12 , G11C5/066 , G11C29/006
摘要： An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.
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公开(公告)号：US5014241A
公开(公告)日：1991-05-07
申请号：US337219
申请日：1989-04-12
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/14 , G11C7/18 , G11C11/4096 , G11C11/4097 , G11C11/4099 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C11/4096 , G11C11/4097 , G11C11/4099 , G11C5/063 , G11C7/14 , G11C7/18
摘要： Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.
摘要翻译： 读出放大器中的每一个耦合到两个位线，另一个位线插在它们之间。 存储在存储器单元中的信息被读出到耦合到每个读出放大器的两个位线中的一个，同时将参考电位读出到另一个位线上。 在两个位线之外，将参考电位分别读出到与两个位线相邻的其它位线上。 存储在存储单元中的信息被读出到两个位线之间的另一位线上。
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27.发明授权Semiconductor memory device having stacked memory capacitors and method for manufacturing the same 失效具有层叠存储电容器的半导体存储器件及其制造方法
公开(公告)号：US4855953A
公开(公告)日：1989-08-08
申请号：US158323
申请日：1988-02-19
IPC分类号： G11C11/404 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/417
CPC分类号： H01L27/10861 , G11C11/404 , H01L27/10829 , H01L29/41725 , H01L29/41766 , H01L29/66181
摘要： A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.
摘要翻译： 动态RAM包括存储器单元的阵列，每个存储器单元包括单个存取晶体管和电荷存储区域。 电荷存储区域包括第一电容器存储器，其包括形成在形成于P型硅衬底中的沟槽的内表面中的用作相对电极的P +区，形成在P +区上的第一电容器电介质膜和用于 作为形成在第一电容器电介质膜上的存储器端子，以及包括公共电极层的第二存储电容器，形成在公共电极层上的第二电容器电介质膜和形成在第二电容器电介质膜上的单元板电极。 存取晶体管的存储器端子和漏极区域通过具有与存储器端子的端部接触的侧壁形状的电极以自对准的方式连接。 因此，不需要在第一电容器电介质膜中形成接触孔，从而可以防止第一电容器电介质膜的电可靠性的降低。 存取晶体管的漏极区可以通过与公共电极层的接触部分进行自对准而形成。
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28.发明申请公开(公告)号：US20090113122A1
公开(公告)日：2009-04-30
申请号：US12261598
申请日：2008-10-30
申请人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
发明人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.
摘要翻译： 在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将 第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。
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29.发明授权Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 失效具有多个放大器组的随机存取存储器，用于在正常和测试模式下进行读写
公开(公告)号：US5867436A
公开(公告)日：1999-02-02
申请号：US803298
申请日：1997-02-20
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。
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30.发明授权Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 失效具有多个放大器组的随机存取存储器，用于在正常和测试模式下进行读写
公开(公告)号：US5636163A
公开(公告)日：1997-06-03
申请号：US632967
申请日：1996-04-16
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。
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