公开(公告)号：US20070047295A1

公开(公告)日：2007-03-01

申请号：US11480242

申请日：2006-06-30

申请人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

IPC分类号： G11C11/00

CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

摘要翻译： 磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体， 写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

公开(公告)号：US20050117388A1

公开(公告)日：2005-06-02

申请号：US10969697

申请日：2004-10-20

申请人： Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： G11C13/02 ,  G11C13/00 ,  G11C16/02 ,  G11C16/12 ,  G11C16/30 ,  G11C29/02 ,  H01L27/105 ,  H01L45/00 ,  G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C29/02 ,  G11C29/028 ,  G11C2013/0078 ,  G11C2029/5006 ,  G11C2213/79

摘要： A write driver circuit including a plurality of programmable fuses for a phase change memory device in which a write operation is correctly performed even in the case where a current output shift in a write current generation circuit; or in the case where a phase change memory cell has a phase change property shift due to an external factor or due a process change. The write driver circuit includes; a write current control unit for outputting a first or second level of voltage selected, by selecting one of a first or second programmable current path, based on whether a first or second selection pulse signal is applied; and a current driving unit for generating a write current controlled by the output voltage of the write current control unit. Each of the first and second programmable current paths includes fuses that can be programmed to adjusted their resistance to adjust the respective selected output voltage to compensate for a current output shift in a write current generation circuit or for a phase change memory cell has a phase change property shift.

摘要翻译： 一种写入驱动器电路，包括用于相变存储器件的多个可编程保险丝，其中即使在写入电流产生电路中的电流输出移位的情况下也正确地执行写入操作; 或者在相变存储单元由于外部因素或由于处理变化而具有相变特性偏移的情况。 写驱动电路包括： 写入电流控制单元，用于通过选择第一或第二可编程电流路径中的一个，基于是施加第一还是第二选择脉冲信号来输出所选择的第一或第二电平电平; 以及电流驱动单元，用于产生由写入电流控制单元的输出电压控制的写入电流。 第一和第二可编程电流路径中的每一个包括熔丝，其可以被编程以调整其电阻以调整相应的选择的输出电压以补偿写入电流产生电路中的电流输出偏移，或者对于相变存储器单元具有相变 财产转移

公开(公告)号：US06714463B2

公开(公告)日：2004-03-30

申请号：US10251739

申请日：2002-09-20

申请人： Gong-Heum Han ,  Choong-Keun Kwak ,  Kyeong-Yoon Bae

发明人： Gong-Heum Han ,  Choong-Keun Kwak ,  Kyeong-Yoon Bae

IPC分类号： G11C700

CPC分类号： G11C8/18 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2281

摘要： A semiconductor memory device is provided to generate a series of pulse signals in response to the activation of an internal chip select signal from an internal chip select buffer when an external chip select signal transitions from an inactive state to an active state. With this configuration, a chip select output time (tco) is more reduced as compared to prior arts. Further, the chip select output time is reduced to be equal to an address access time (tAA) because a designer can control the chip select output time. As a result, the whole access time of the semiconductor memory device can be reduced.

摘要翻译： 半导体存储器件被提供以当外部芯片选择信号从非活动状态转换到激活状态时，响应于来自内部芯片选择缓冲器的内部芯片选择信号的激活而产生一系列脉冲信号。 利用这种配置，与现有技术相比，芯片选择输出时间（tco）更多地减少。 此外，芯片选择输出时间减小到等于地址访问时间（tAA），因为设计者可以控制芯片选择输出时间。 结果，可以减少半导体存储器件的整个访问时间。

公开(公告)号：US6026039A

公开(公告)日：2000-02-15

申请号：US215576

申请日：1998-12-17

申请人： Du-Eung Kim ,  Choong-Keun Kwak ,  Yun-Seung Shin

发明人： Du-Eung Kim ,  Choong-Keun Kwak ,  Yun-Seung Shin

IPC分类号： H01L21/822 ,  G01R31/26 ,  G01R31/28 ,  G11C29/02 ,  G11C29/50 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C29/022 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/2602 ,  G11C2029/5006

摘要： A parallel test circuit for a semiconductor memory device includes multiple data input pads, multiple data input buffers respectively connected to the data input pads for receiving write data in response to a chip selection signal during normal operation, and a switching circuit for electrically connecting the data input pads to each other in response to a current leakage test signal applied to the circuit. The circuit enables the detection of leakage current in the input data buffers at the same time that a parallel data writing test is performed, thereby reducing the total time required to test the device.

摘要翻译： 一种用于半导体存储器件的并行测试电路包括多个数据输入焊盘，分别连接到数据输入焊盘的多个数据输入缓冲器，用于在正常操作期间响应芯片选择信号接收写入数据;以及切换电路，用于电连接数据 响应于施加到电路的电流泄漏测试信号，输入焊盘彼此相连。 该电路能够在执行并行数据写入测试的同时检测输入数据缓冲器中的漏电流，从而减少测试器件所需的总时间。

公开(公告)号：US5959907A

公开(公告)日：1999-09-28

申请号：US28150

申请日：1998-02-23

申请人： Du-Eung Kim ,  Choong-Keun Kwak

发明人： Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C29/04 ,  G11C7/00 ,  G11C8/00 ,  G11C29/00

CPC分类号： G11C11/418 ,  G11C29/785 ,  G11C29/83

摘要： A redundancy circuit for a semiconductor device comprises a circuit having variable impedance changed in accordance with a chip selecting signal. The variable impedance circuit has a low impedance when the chip selecting signal is at a low level and a high impedance when the chip selecting signal is at a high level. Therefore, when the device is in a standby state, no static current flows, and when the chip is in an active state current of less than several micro amperes flows. Thus, the power dissipation of the redundancy circuit can be reduced.

摘要翻译： 用于半导体器件的冗余电路包括根据芯片选择信号而改变可变阻抗的电路。 当芯片选择信号处于低电平时，可变阻抗电路具有低阻抗，并且当芯片选择信号处于高电平时具有高阻抗。 因此，当器件处于待机状态时，不会流动静电流，并且当芯片处于活动状态时，电流小于几微安流动。 因此，可以减少冗余电路的功率消耗。

公开(公告)号：US5576999A

公开(公告)日：1996-11-19

申请号：US491348

申请日：1995-06-30

申请人： Jae-Chul Kim ,  Choong-Keun Kwak

发明人： Jae-Chul Kim ,  Choong-Keun Kwak

IPC分类号： G11C29/00 ,  G11C29/48 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/48

摘要： A redundancy circuit of the semiconductor memory device having a normal memory cell array for storing data, a redundant memory cell for repairing the fail cells in the normal memory, cell array, a normal decoder for receiving addresses and designating the normal memory cell, a redundancy decoder for selecting the redundant memory cell. The circuit includes a control part which is controlled by a control clock and has fuses for programming fail addresses of the addresses, to be applied, a transmission part which is controlled by an output signal of the control part and has a first path for outputting addresses in-phase with the addresses and a second path for outputting addresses out of phase with the addresses, thereby selecting the first path before repair to select both the normal memory cell and redundant memory cell by the normal and redundancy decoders, and cutting off the fuses corresponding to the fail addresses and selecting the second path during the repair to select the redundant memory cell by the redundancy decoder, thus enabling burn-in of both the normal memory cell and redundant memory cell during the burn-in test.

摘要翻译： 具有用于存储数据的正常存储单元阵列的半导体存储器件的冗余电路，用于修复正常存储器中的故障单元的冗余存储单元，单元阵列，用于接收地址和指定正常存储单元的正常解码器，冗余 用于选择冗余存储器单元的解码器。 电路包括由控制时钟控制的控制部分，并且具有用于编程要应用的地址的失败地址的熔丝，由控制部分的输出信号控制的发送部分，并且具有用于输出地址的第一路径 与地址同相，以及用于输出地址与地址异相的第二路径，从而在修复之前选择第一路径以通过正常和冗余解码器选择正常存储器单元和冗余存储器单元，并且切断熔丝 对应于故障地址并且在修复期间选择第二路径以通过冗余解码器选择冗余存储器单元，从而在老化测试期间能够老化正常存储器单元和冗余存储器单元。

公开(公告)号：US07994493B2

公开(公告)日：2011-08-09

申请号：US12196137

申请日：2008-08-21

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L29/04 ,  H01L47/00

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.

摘要翻译： 相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。 字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。 第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。 多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

公开(公告)号：US20110053293A1

公开(公告)日：2011-03-03

申请号：US12915335

申请日：2010-10-29

申请人： Woo-Yeong CHO ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

发明人： Woo-Yeong CHO ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

IPC分类号： H01L21/62

CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

摘要翻译： 磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体， 写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

公开(公告)号：US07710767B2

公开(公告)日：2010-05-04

申请号：US11969326

申请日：2008-01-04

申请人： Beak-Hyung Cho ,  Do-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

发明人： Beak-Hyung Cho ,  Do-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

摘要翻译： 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到 多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

公开(公告)号：US20080080240A1

公开(公告)日：2008-04-03

申请号：US11902424

申请日：2007-09-21

申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

IPC分类号： G11C16/00

CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4063 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.

摘要翻译： 公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。 非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器 对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。