公开(公告)号：US08892381B2

公开(公告)日：2014-11-18

申请号：US13044320

申请日：2011-03-09

申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

IPC分类号： G01R31/26 ,  G06F19/00 ,  G01R31/319 ,  G01R31/3185

CPC分类号： G01R31/318511 ,  G01R31/31926

摘要： A test apparatus that tests a plurality of devices under test formed on a wafer under test includes a test substrate that faces the wafer under test and is electrically connected to the devices under test, a programmable device that is provided on the test substrate and changes a logic relationship of output logic data with respect to input logic data, according to program data supplied thereto, a plurality of input/output circuits that are provided on the test substrate to correspond to the devices under test and that each supply the corresponding device under test with a test signal corresponding to the output logic data of the programmable device, and a judging section that judges pass/fail of each device under test, based on operation results of each device under test according to the test signal.

摘要翻译： 测试在被测晶片上形成的多个待测器件的测试装置包括面向被测晶片并与被测器件电连接的测试基板，设置在测试基板上的可编程器件， 输出逻辑数据相对于输入逻辑数据的逻辑关系，根据提供给其的程序数据，多个输入/输出电路，设置在测试基板上以对应于被测器件，并且每个输入/输出电路提供相应的被测器件 具有与可编程装置的输出逻辑数据相对应的测试信号，以及判定部，根据测试信号，根据被测设备的运算结果，判定各被测设备的通过/失败。

公开(公告)号：US20140172280A1

公开(公告)日：2014-06-19

申请号：US14235271

申请日：2012-07-26

申请人： Kenichiroh Ogata ,  Daisuke Watanabe ,  Takashi Okamoto

发明人： Kenichiroh Ogata ,  Daisuke Watanabe ,  Takashi Okamoto

IPC分类号： F02D41/14

CPC分类号： F02D41/1493 ,  B60W10/04 ,  F02D13/0242 ,  F02D35/027 ,  F02D41/0007 ,  F02D41/3017 ,  F02D41/40 ,  F02D2041/001 ,  F02D2041/1432 ,  F02D2041/288 ,  F02D2200/025 ,  F02P5/04 ,  G01H17/00 ,  G01M15/12 ,  Y02T10/128 ,  Y02T10/144 ,  Y02T10/18 ,  Y02T10/44

摘要： Although a method for changing a combustion method taking place in an internal combustion engine depending on running condition is proposed, it can be considered that conditions under which a combustion noise occurs naturally differ with different methods. A detection method of prior art is not compatible with different combustion methods and the accuracy of combustion noise detection was low. Accurate combustion noise detection is enabled by identifying a combustion mode taking place in the internal combustion engine, selecting a sensed frequency or frequency band of a combustion noise sensor that detects a combustion noise in a combustion chamber of the internal combustion engine according to the combustion mode, and detecting a combustion noise.

摘要翻译： 虽然提出了根据运行条件改变在内燃机中发生的燃烧方法的方法，但是可以认为燃烧噪声发生的条件自然地因不同的方法而不同。 现有技术的检测方法与不同的燃烧方法不兼容，燃烧噪声检测的精度低。 通过识别在内燃机中发生的燃烧模式来实现准确的燃烧噪声检测，根据燃烧模式选择检测内燃机的燃烧室中的燃烧噪声的燃烧噪声传感器的感测频率或频带 ，并且检测燃烧噪声。

公开(公告)号：US20130271577A1

公开(公告)日：2013-10-17

申请号：US13976200

申请日：2011-12-22

申请人： Daisuke Watanabe ,  Shinji Uchiyama ,  Daisuke Kotake

发明人： Daisuke Watanabe ,  Shinji Uchiyama ,  Daisuke Kotake

IPC分类号： H04N13/02

CPC分类号： H04N13/275 ,  G06T7/75 ,  G06T2207/10004 ,  G06T2207/10028

摘要： An information processing apparatus includes a model storing unit configured to store a three-dimensional form model for acquiring the position and posture of a measurement target object, an image acquiring unit configured to acquire an image of the measurement target object, a first position and posture acquiring unit configured to acquire a first position and posture of the three-dimensional form model in a first coordinate system on the basis of a first geometric feature of the three-dimensional form model and a first geometric feature within the image, and a second position and posture acquiring unit configured to acquire a second position and posture of the three-dimensional form model in a second coordinate system that is different from the first coordinate system on the basis of a second geometric feature of the three-dimensional form model and a second geometric feature within the image and the first position and posture.

摘要翻译： 一种信息处理设备，包括：模型存储单元，被配置为存储用于获取测量目标对象的位置和姿势的三维形式模型;图像获取单元，被配置为获取测量目标对象的图像，第一位置和姿势 获取单元，被配置为基于所述三维形式模型的第一几何特征和所述图像内的第一几何特征获取第一坐标系中的所述三维形式模型的第一位置和姿势，以及第二位置 以及姿势获取单元，被配置为基于所述三维形式模型的第二几何特征，在与所述第一坐标系不同的第二坐标系中获取所述三维形式模型的第二位置和姿势;以及第二 图像内的几何特征和第一位置和姿势。

公开(公告)号：US08549837B2

公开(公告)日：2013-10-08

申请号：US12958166

申请日：2010-12-01

申请人： Kenji Ushijima ,  Hirokazu Hasegawa ,  Yasushi Nakatani ,  Keishi Kitabatake ,  Yasushi Kusunoki ,  Toshiaki Kamo ,  Yoshitaka Nakamura ,  Daisuke Watanabe ,  Hiroki Shimoji ,  Masami Negami

发明人： Kenji Ushijima ,  Hirokazu Hasegawa ,  Yasushi Nakatani ,  Keishi Kitabatake ,  Yasushi Kusunoki ,  Toshiaki Kamo ,  Yoshitaka Nakamura ,  Daisuke Watanabe ,  Hiroki Shimoji ,  Masami Negami

IPC分类号： F01N3/08

CPC分类号： F01N13/1822 ,  F01N3/10 ,  F01N13/08 ,  F01N13/10 ,  F01N13/1816 ,  F01N2340/04 ,  Y02A50/2322

摘要： An exhaust upstream section (48) of an exhaust apparatus (E) comprises a plurality of branch pipe portions (32), a plurality of intermediate collector pipe portions (33), a final collector pipe portion (34), and an exhaust gas-purifying unit (40). The exhaust gas-purifying unit (40) is disposed on a vehicle-rear side of an engine (1) to allow a gas passage thereinside to extend approximately in vehicle-widthwise direction, in top plan view. Each of the plurality of intermediate collector pipe portions (33) curves to allow an exhaust downstream region of the intermediate collector pipe portion (33) to be oriented toward one side or the other side of the vehicle-widthwise direction, in top plan view, and the final collector pipe portion (34) curves to allow an exhaust downstream region of the final collector pipe portion (34) to be oriented toward a vehicle-front side, in top plan view.

摘要翻译： 排气装置（E）的排气上游部（48）包括多个分支管部（32），多个中间收集管部（33），最终收集管部（34） 净化单元（40）。 排气净化单元（40）设置在发动机（1）的车辆后侧，以允许其内部的气体通道在顶部平面图中大致沿车辆宽度方向延伸。 多个中间收集管部33中的每一个弯曲以允许中间收集管部33的排气下游区域在俯视图中朝向车宽方向的一侧或另一侧取向， 在顶部平面图中，最终收集管部（34）弯曲成允许最终收集管部（34）的排气下游区域朝向车辆前侧。

公开(公告)号：US08537935B2

公开(公告)日：2013-09-17

申请号：US12532132

申请日：2008-03-18

申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

IPC分类号： H03D3/18 ,  H03D3/24

CPC分类号： H04L7/033 ,  G01R31/31727 ,  G01R31/31937 ,  H03L7/0812 ,  H04L7/0037

摘要： A change-point detection circuit 16 extracts a clock signal from serial data, input data. A variable delay circuit provides a delay in accordance with a delay control signal to a reference signal having a predetermined frequency, so that the phase of the reference signal is shifted on the basis of an initial delay. An input latch circuit latches internal serial data by using an output signal of the variable delay circuit as a strobe signal. A phase comparator matches the frequencies of the clock signal and the strobe signal with each other, and generates phase difference data in accordance with a phase difference between the two signals. A loop filter integrates the phase difference data generated by the phase comparator and outputs it as the delay control signal. The phase shift amount acquisition unit acquires a phase shift amount based on the delay control signal, the phase shift amount being based on the initial delay provided to the reference signal by the variable delay circuit.

摘要翻译： 变化点检测电路16从串行数据，输入数据中提取时钟信号。 可变延迟电路根据具有预定频率的参考信号的延迟控制信号提供延迟，使得参考信号的相位基于初始延迟而偏移。 输入锁存电路通过使用可变延迟电路的输出信号作为选通信号来锁存内部串行数据。 相位比较器将时钟信号和选通信号的频率相互匹配，并根据两个信号之间的相位差产生相位差数据。 环路滤波器对相位比较器产生的相位差数据进行积分，并将其作为延迟控制信号输出。 相移量获取单元基于延迟控制信号获取相移量，相移量基于由可变延迟电路提供给参考信号的初始延迟。

公开(公告)号：US08466702B2

公开(公告)日：2013-06-18

申请号：US12953352

申请日：2010-11-23

申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

IPC分类号： G01R31/20 ,  G01R31/02

CPC分类号： G01R31/2889

摘要： A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon.

摘要翻译： 一种在被测晶片上测试被测试的多个待测芯片的测试系统，所述测试系统包括多个测试基板，所述多个测试基板布置在重叠层中，并且每个具有多个测试电路，每个测试电路的功能是针对每个晶片 ，形成在其上 多个连接部，其将与测试用芯片电连接的测试电路形成在一个测试基板上; 以及控制每个测试电路的控制装置。 每个测试基板具有在其上形成的具有对于每个基板预定的功能的测试电路。

公开(公告)号：US08378700B2

公开(公告)日：2013-02-19

申请号：US12953362

申请日：2010-11-23

申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

IPC分类号： G01R31/20

CPC分类号： G01R31/2884 ,  G01R31/2831

摘要： Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals.

摘要翻译： 提供了一种用于测试形成在半导体晶片上的多个半导体芯片的测试晶片单元，该测试晶片单元包括：具有对应于半导体晶片形状的形状的测试晶片; 以及形成在所述测试晶片上的多个测试电路，每个测试电路被提供以对应于所述多个半导体芯片中的两个或更多个并且测试所述两个或更多个半导体芯片。 测试晶片单元可以包括与多个半导体芯片的测试端子成一一关系的在测试晶片上形成的多个连接端子，其中多个连接端子中的每一个连接到相应的一个测试端子。

公开(公告)号：US08375340B2

公开(公告)日：2013-02-12

申请号：US12952112

申请日：2010-11-22

申请人： Daisuke Watanabe ,  Masakatsu Suda ,  Toshiyuki Okayasu

发明人： Daisuke Watanabe ,  Masakatsu Suda ,  Toshiyuki Okayasu

IPC分类号： G06F17/50

CPC分类号： G01R31/318511 ,  G01R31/31718

摘要： A test substrate manufacturing apparatus comprising a test circuit database that stores circuit data of a plurality of types of test circuits in association with a plurality of types of testing content; a definition information storing section that stores definition information defining arrangements of device pads of devices under test and testing content to be performed for each of the device pads; and a lithography data generating section that generates lithography data for the test substrate by (i) selecting, from the test circuit database, circuit data of each test circuit to be connected to a device pad based on the testing content defined by the definition information stored in the definition information storing section and (ii) determining positions on the test substrate where the test circuits corresponding to the selected circuit data are formed using lithography, based on the arrangements of the device pads as defined by the definition information.

摘要翻译： 一种测试基板制造装置，包括：与多种测试内容相关联地存储多种类型的测试电路的电路数据的测试电路数据库; 定义信息存储部分，其存储定义要定义的装置的装置的定义信息，并且对每个装置焊盘执行测试内容; 以及光刻数据生成部，其通过以下步骤生成用于所述测试基板的光刻数据：（i）基于由所存储的所述定义信息定义的测试内容，从所述测试电路数据库中选择要连接到设备焊盘的每个测试电路的电路数据 在定义信息存储部分中，以及（ii）基于由定义信息定义的装置焊盘的布置，确定测试基板上的位置，其中使用光刻形成与所选择的电路数据相对应的测试电路。

公开(公告)号：US20120319794A1

公开(公告)日：2012-12-20

申请号：US13588823

申请日：2012-08-17

申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

IPC分类号： H03K7/00 ,  H03K9/00

CPC分类号： H04L27/34 ,  G01R31/31924 ,  H04L25/4917 ,  H04L27/362 ,  H04L27/38

摘要： A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.

摘要翻译： 测试装置包括以多个通道为增量提供的数字调制器。 基带信号发生器使用可以调整定时信号的定时信号来执行数据输入的重新定时作为同相（正交）分量的调制信号，从而生成基带信号。 驱动器产生具有与从基带信号发生器输出的基带信号对应的电平的多值数字信号。 乘法器用多值数字信号对载波信号进行幅度调制。 加法器对乘法器的输出信号求和。

公开(公告)号：US08270225B2

公开(公告)日：2012-09-18

申请号：US12532134

申请日：2008-03-18

申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

IPC分类号： G11C7/10

CPC分类号： G01R31/3191 ,  G01R31/31937

摘要： A variable delay circuit provides an adjustable delay to a strobe signal. An input latch circuit latches each bit data included in internal serial data by a strobe signal delayed by the variable delay circuit. A delay set unit adjusts a delay amount provided to the strobe signal by the variable delay circuit. While a calibration operation is being executed in which a known calibration pattern is inputted as serial data, the delay set unit statistically acquires output latch data of the input latch circuit, and adjusts the delay amount such that probabilities of occurrence of 1 and 0 becomes a predetermined ratio.

摘要翻译： 可变延迟电路为选通信号提供可调延迟。 输入锁存电路通过可变延迟电路延迟的选通信号来锁存内部串行数据中包含的每个位数据。 延迟设定单元通过可变延迟电路来调整提供给选通信号的延迟量。 当正在执行其中输入已知校准图案作为串行数据的校准操作时，延迟设置单元统计地获取输入锁存电路的输出锁存数据，并调整延迟量，使得出现1和0的概率变为 预定比例。