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公开(公告)号：US06681313B1
公开(公告)日：2004-01-20
申请号：US09566319
申请日：2000-05-08
IPC分类号： G06F1208
CPC分类号： G06F12/1027
摘要： In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to tables entries in which the entries are addressed after adding a plurality of address parts wherein the plurality is two (2) or (3). Particularly, a smaller and/or faster adder is used having, for example, only n=2 ports in the time critical path. In order to make the exact address calculation, during array accesses, a multiplexor is implemented to decide, after the TLB arrays are accessed for preselection, which of a plurality of possible entries has to be taken.
摘要翻译： 在用于在虚拟存储器系统中进行虚拟地址转换并实现诸如翻译后备缓冲器之类的表的系统中，能够更快地访问在其中条目被寻址的表条目的系统和方法，其中添加了多个地址部分，其中多个 是二（2）或（3）。 特别地，使用较小和/或更快的加法器，其具有例如在时间关键路径中仅n = 2个端口。 为了进行精确的地址计算，在阵列访问期间，实现多路复用器以在对预选择的TLB阵列进行访问之后决定必须采取多个可能的条目中的哪一个。
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公开(公告)号：US08422313B2
公开(公告)日：2013-04-16
申请号：US13284480
申请日：2011-10-28
CPC分类号： G11C7/18 , G11C7/12 , G11C29/846 , G11C2207/005
摘要： In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.
摘要翻译： 在可以并行访问的存储单元的阵列系统中降低功耗的电路中，本地评估电路连接到存储器单元阵列系统的存储单元和全局位线。 选择电路将全局位线分割成全局位线的上部和下部。 选择电路适于接收早期设定的预测信号，并且基于早期设定的预测信号将全局位线的上部连接到全局位线的下部。 早期设置的预测信号指示是否正在读取包括存储器单元的一组存储单元。 该电路还包括连接到全局位线的下部的N：1多路复用器，以接收全局位线的下部作为输入。
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公开(公告)号：US07755394B2
公开(公告)日：2010-07-13
申请号：US12196427
申请日：2008-08-22
申请人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
发明人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.
摘要翻译： 描述了将电平移位功能与门控复位组合的电路（01），其具有由较低电压（VD）提供的输入和在其输出端（05）以较高电压（VC）驱动的简单逻辑功能。 所述电路（01）包括门控复位方案加上用于逻辑功能的装置（10,30,40）。
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公开(公告)号：US20080298137A1
公开(公告)日：2008-12-04
申请号：US12053128
申请日：2008-03-21
CPC分类号： G11C29/12 , G11C11/41 , G11C2029/1204
摘要： A domino read bit line structure (20) integral to an SRAM array (1, 2) with thirty-two word lines or less to access SRAM cells divided into two groups (3, 4, 90, 100) is described. The bit line structure (20) includes a dynamic bit decode multiplexer (11, 40) and two NAND circuits (5, 80) used to combine the two groups (3, 4, 90, 100), wherein in order to reduce power consumption the two NANDS (80) drive the dynamic bit decode multiplexer (40) directly, such that true and complement dynamic outputs (rt, rc) drive a set-reset latch (50) to convert the dynamic outputs (rt, rc) to a single static signal (doc), wherein the output of the set-reset latch (50) is already static so that the set-reset latch (50) acts as an effective array output latch (7).
摘要翻译： 描述了与具有32个字线或更少的SRAM阵列（1,2）积分的多米诺读取位线结构（20），以访问分成两组（3,4,90,100）的SRAM单元。 位线结构（20）包括动态位解码多路复用器（11,40）和用于组合两组（3,490,100）的两个NAND电路（5,80），其中为了降低功耗 两个NANDS（80）直接驱动动态位解码多路复用器（40），使得真实和补充动态输出（rt，rc）驱动设置复位锁存器（50）以将动态输出（rt，rc）转换为 单个静态信号（doc），其中所述设置复位锁存器（50）的输出已经是静态的，使得所述设置复位锁存器（50）用作有效阵列输出锁存器（7）。
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25.发明授权Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates 失效通过在复杂的动态多米诺式CMOS门中应用固有的并行性来减少电荷共享公开(公告)号：US07095252B2
公开(公告)日：2006-08-22
申请号：US10896836
申请日：2004-07-22
申请人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
发明人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
IPC分类号： H03K19/096 , H03K19/00 , H03K19/20 , H03K19/094
CPC分类号： H03K19/0963
摘要： The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
摘要翻译： 本发明涉及计算机处理器的动态硬件逻辑。 特别地，本发明涉及一种用于操作实现具有减少的电荷共享的预定逻辑功能的动态逻辑电路的方法和相应的系统。 为了进一步减少电荷共享，建议提供预定数量的预先设计的切换布置（24,26,28），其实现与输入变量（A，B，C）的不同组合分布相同的逻辑功能，其中 每个布置连接在较高电位的所述预充电节点和较低电位之间。
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26.发明申请Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates 失效通过在复杂的动态多米诺式CMOS门中应用固有的并行性来减少电荷共享公开(公告)号：US20050040861A1
公开(公告)日：2005-02-24
申请号：US10896836
申请日：2004-07-22
申请人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
发明人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
IPC分类号： H03K19/096 , H03K19/20
CPC分类号： H03K19/0963
摘要： The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
摘要翻译： 本发明涉及计算机处理器的动态硬件逻辑。 特别地，本发明涉及一种用于操作实现具有减少的电荷共享的预定逻辑功能的动态逻辑电路的方法和相应的系统。 为了进一步减少电荷共享，建议提供预定数量的预先设计的切换布置（24,26,28），其实现与输入变量（A，B，C）的不同组合分布相同的逻辑功能，其中 每个布置连接在较高电位的所述预充电节点和较低电位之间。
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公开(公告)号：US08086657B2
公开(公告)日：2011-12-27
申请号：US12099973
申请日：2008-04-09
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F7/50
CPC分类号： H03K19/0941 , H03K19/0008
摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译： 一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。 优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。 优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。
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公开(公告)号：US07224190B2
公开(公告)日：2007-05-29
申请号：US11009830
申请日：2004-12-10
申请人： Wilhelm Haller , Rolf Sautter , Monika Strohmer , Klaus Thumm
发明人： Wilhelm Haller , Rolf Sautter , Monika Strohmer , Klaus Thumm
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.
摘要翻译： 本发明涉及硬件逻辑电路领域，特别涉及在计算机处理器中实现的动态硬件逻辑，更具体地，涉及一种集成电路，其包括实现具有多个晶体管堆叠的预定逻辑功能的动态逻辑功能，所述集成电路 电路包括在所述逻辑功能实现的输入处的预充电节点，连接到所述逻辑功能的输出节点的输出锁存器，用于稳定所述逻辑功能的评估结果。 本发明提供了具有锁存器的这种集成动态电路，其即使在涉及复杂逻辑功能的情况下也被保护以防止不稳定性，这些功能被评估，并且其输出状态由所述输出锁存器保存。
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公开(公告)号：US06496398B2
公开(公告)日：2002-12-17
申请号：US09683269
申请日：2001-12-06
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： The present invention relates to content addressable memory (CAM), particularly, to a CAM having its memory array, which contains a plurality of memory locations, being divided into at least a first and a second memory block (100, 102), whereby the first and second memory block (100, 102) are formed by a first and second portion of each of said memory locations, respectively. The CAM further comprises a first set of compare lines (115) and a first set-of match lines (116) associated to said first memory block (100), and a second set of compare lines (117) and a second set of match lines (118) associated to said second memory block (102), and pre-charge units (112, 114) for charging said match lines before a comparison operation. The present invention provides an improved CAM which allows flagging of memory locations of which the content only partially matches a given comparison value. This is achieved by a CAM according to the above features using the pre-charge state of the match lines (116, 118) as a logically valid state.
摘要翻译： 本发明涉及内容可寻址存储器（CAM），特别是涉及具有其存储器阵列的CAM（其包含多个存储器位置）的CAM，其被划分为至少第一和第二存储器块（100,102），由此， 第一和第二存储器块（100,102）分别由每个所述存储单元的第一和第二部分形成。 CAM还包括与第一存储块（100）相关联的第一组比较线（115）和第一组匹配线（116），以及第二组比较线（117）和第二组匹配 与所述第二存储块（102）相关联的线路（118）以及用于在比较操作之前对所述匹配线路进行充电的预充电单元（112,114）。 本发明提供一种改进的CAM，其允许标记其内容仅部分匹配给定比较值的存储器位置。 这通过根据上述使用匹配线（116,118）的预充电状态作为逻辑有效状态的CAM来实现。
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公开(公告)号：US20130128684A1
公开(公告)日：2013-05-23
申请号：US13466973
申请日：2012-05-08
摘要： A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication.
摘要翻译： 存储器阵列可以配置有头部装置以减少泄漏。 标题装置与解码器耦合以接收存储器地址指示的至少第一部分，并被耦合以从电源接收电流。 每个头部装置适于从电源向与存储器地址指示的第一部分指示的存储体相对应的一组字线驱动器提供电力。 每个逻辑设备被耦合以从解码器接收存储器地址指示的至少第二部分。 每个逻辑设备被耦合以激活与由存储器地址指示的第二部分指示的字线的字线驱动器耦合的字线驱动器。
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