公开(公告)号：US08014200B2

公开(公告)日：2011-09-06

申请号：US12420659

申请日：2009-04-08

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/34 ,  G11C14/00

CPC分类号： G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

摘要翻译： 描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体 将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 所述捕获层包括第一和第二存储位置，其被配置为独立于彼此独立地存储作为非易失性存储器的数据; 以及位于捕获层上方的控制门。

公开(公告)号：US20110044110A1

公开(公告)日：2011-02-24

申请号：US12915706

申请日：2010-10-29

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括从衬底延伸的翅片结构，所述鳍结构包括具有第一导电类型的浮置衬底区域，其被配置为将数据存储为易失性存储器; 第一和第二区域与浮动衬底区域相接合，第一和第二区域中的每一个具有第二导电类型; 位于浮置衬底区域的相对侧的第一和第二浮栅或俘获层; 位于所述浮置衬底区域和所述浮置栅极或俘获层之间的第一绝缘层，所述浮置栅极或俘获层被配置为接收由所述易失性存储器存储的数据的传送，并将所述数据作为非易失性存储器存储在所述浮置栅极或俘获层中 在中断存储器单元的电源时; 围绕浮动栅极或捕获层和浮置衬底区域的控制栅极; 以及位于所述浮置栅极或俘获层之间的第二绝缘层和所述控制栅极; 所述衬底包括将所述浮置衬底区域与所述隔离层下方的所述衬底的一部分隔离的隔离层。

公开(公告)号：US20100246284A1

公开(公告)日：2010-09-30

申请号：US12797320

申请日：2010-06-09

申请人： Yuniarto Widjaja ,  Zvi Or-Bach

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C5/14 ,  H01L27/06 ,  G11C7/00

CPC分类号： G11C11/404 ,  G11C11/565 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11521 ,  H01L29/7841 ,  H01L29/7881

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

摘要翻译： 半导体存储单元包括被配置为被充电到指示存储单元的状态的电平的浮动体区域; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 位于所述第一和第二区域之间的门; 以及背偏置区域，被配置为将电荷注入或从所述浮体区域中提取电荷，以维持存储单元的所述状态。 将背偏置施加到背偏置区域将电荷泄漏偏离浮体，并对电池执行保持操作。 单元可以是多级单元。 公开了用于制造存储器件的存储器单元阵列。

公开(公告)号：US07800159B2

公开(公告)日：2010-09-21

申请号：US11923515

申请日：2007-10-24

申请人： Yuniarto Widjaja ,  Henry A. O'M'Mani ,  Prateep Tuntasood ,  Bomy Chen

发明人： Yuniarto Widjaja ,  Henry A. O'M'Mani ,  Prateep Tuntasood ,  Bomy Chen

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A plurality of non-volatile memory cell units are arranged in rows and columns in a single crystalline semiconductor substrate of a first conductivity type. Each cell unit has a first region of a second conductivity type in the substrate along the planar surface, and a second region of the second conductivity, spaced apart from the first region, with a channel region therebetween. The channel region has a first portion adjacent to the first region, a third portion adjacent to the second region and a second portion therebetween. A first and second floating gates are over the first portion and third portion respectively and are insulated therefrom. A first and second control gates are over the first and second floating gates respectively and are capacitively coupled thereto. A first and second erase gates are over the first and second regions respectively and are insulated therefrom. A word line is over the second portion and is insulated therefrom. Electrical contacts to the array are made along the extremities of the array.

摘要翻译： 多个非易失性存储单元单元以第一导电类型的单晶半导体衬底中的行和列布置。 每个单元单元具有沿着平面的基板中的第二导电类型的第一区域和与第一区域间隔开的第二导电体的第二区域，其间具有沟道区域。 通道区域具有与第一区域相邻的第一部分，与第二区域相邻的第三部分和在其间的第二部分。 第一和第二浮动栅极分别在第一部分和第三部分之上，并与之绝缘。 第一和第二控制栅极分别在第一和第二浮置栅极之上并与其电容耦合。 第一和第二擦除栅极分别在第一和第二区域之上并与之绝缘。 字线在第二部分之上并与之绝缘。 阵列的电触点沿着阵列的末端进行。

公开(公告)号：US07760548B2

公开(公告)日：2010-07-20

申请号：US11998311

申请日：2007-11-29

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00

CPC分类号： H01L27/10802 ,  G11C11/40 ,  G11C11/404 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在基板的第二位置处嵌入基板并具有第二导电类型，使得具有第一导电类型的基板的至少一部分位于第一和第二位置之间，并且用作浮体以存储 易失性存储器中的数据; 位于所述第一和第二位置之间且位于所述基板的表面之上并且通过绝缘层与所述表面绝缘的浮栅或捕获层; 浮动栅极或俘获层被配置为在中断对存储器单元的电力时，接收由易失性存储器存储的数据的传输并将数据作为非易失性存储器存储在浮动栅极或俘获层中; 以及位于浮置栅极或俘获层上方的控制栅极和位于浮置栅极或捕获层与控制栅极之间的第二绝缘层。

公开(公告)号：US20090251966A1

公开(公告)日：2009-10-08

申请号：US12420659

申请日：2009-04-08

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  H01L27/108 ,  G11C16/04

CPC分类号： G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

摘要翻译： 描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体 将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 所述捕获层包括第一和第二存储位置，其被配置为独立于彼此独立地存储作为非易失性存储器的数据; 以及位于捕获层上方的控制门。

公开(公告)号：US07470949B1

公开(公告)日：2008-12-30

申请号：US11828213

申请日：2007-07-25

申请人： Bomy Chen ,  Yuniarto Widjaja ,  Jack Edward Frayer ,  Felix (Ying-Kit) Tsui

发明人： Bomy Chen ,  Yuniarto Widjaja ,  Jack Edward Frayer ,  Felix (Ying-Kit) Tsui

IPC分类号： H01L27/108

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

摘要： A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.

摘要翻译： 非易失性存储单元具有用于在其上存储电荷的电荷捕获层。 电池是第一导电性衬底中的双向电池。 电池具有两个间隔开的沟槽。 在每个沟槽内，其底部是第二导电性的区域。 一个通道从一个沟槽底部的一个区域沿着该沟槽的侧壁延伸到衬底的顶部平坦表面，并且沿相邻沟槽的侧壁延伸到相邻沟槽底部的区域 。 捕获层沿着两个沟槽中的每一个的侧壁。 控制栅极位于每个沟槽中，每个沟槽沿着侧壁电容耦合到捕获层，并且在沟槽的底部与区域电容耦合。 每个沟槽可以存储多个位。

公开(公告)号：US20080123418A1

公开(公告)日：2008-05-29

申请号：US11998311

申请日：2007-11-29

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/10802 ,  G11C11/40 ,  G11C11/404 ,  G11C14/0018 ,  G11C16/0416 ,  G11C2211/4016 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在基板的第二位置处嵌入基板并具有第二导电类型，使得具有第一导电类型的基板的至少一部分位于第一和第二位置之间，并且用作浮体以存储 易失性存储器中的数据; 位于所述第一和第二位置之间且位于所述基板的表面之上并且通过绝缘层与所述表面绝缘的浮栅或捕获层; 浮动栅极或俘获层被配置为在中断对存储器单元的电力时，接收由易失性存储器存储的数据的传输并将数据作为非易失性存储器存储在浮动栅极或俘获层中; 以及位于浮置栅极或俘获层上方的控制栅极和位于浮置栅极或捕获层与控制栅极之间的第二绝缘层。

公开(公告)号：US20060285394A1

公开(公告)日：2006-12-21

申请号：US11487135

申请日：2006-07-14

申请人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Dang ,  Hung Nguyen ,  Sang Nguyen

发明人： Alexander Kotov ,  Yuniarto Widjaja ,  Tho Dang ,  Hung Nguyen ,  Sang Nguyen

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

摘要翻译： 公开了一种消除程序减速并增强对非易失性浮动栅极存储单元的编程干扰的阻力的方法。 该方法消除或最小化孔位移电流的影响。 这可以通过例如增加施加到高电压端子的高编程电压的上升时间来实现。 或者，非易失性浮栅存储单元的晶体管可以被截止，直到施加到高电压端子的电压达到编程电压。 这可以通过例如通过延迟施加到低电压端子或控制栅极的电压来导通晶体管，直到高压端子处的电压已经超过斜坡上升电压并达到电平编程电压。

公开(公告)号：US10553683B2

公开(公告)日：2020-02-04

申请号：US15724989

申请日：2016-04-27

申请人： Jin-Woo Han ,  Yuniarto Widjaja ,  Zvi Or-Bach ,  Dinesh Maheshwari ,  Zeno Semiconductor, Inc.

发明人： Jin-Woo Han ,  Yuniarto Widjaja ,  Zvi Or-Bach ,  Dinesh Maheshwari

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  G11C16/10 ,  G11C16/26 ,  H01L27/24 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L29/32 ,  H01L21/265 ,  H03K19/20 ,  H03K19/21 ,  H01L29/06 ,  H03K19/0948 ,  G11C16/04 ,  G11C13/00

摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.