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    METHOD AND APPARATUS FOR OPTIMIZING AN OPTICAL PROXIMITY CORRECTION MODEL
    21.
    发明申请
    METHOD AND APPARATUS FOR OPTIMIZING AN OPTICAL PROXIMITY CORRECTION MODEL 有权
    用于优化光学近似校正模型的方法和装置

    公开(公告)号：US20090249261A1

    公开(公告)日：2009-10-01

    申请号：US12054572

    申请日：2008-03-25

    申请人： HUNG-EIL KIM ,  Eun-Joo Lee ,  Christopher A. Spence

    发明人： HUNG-EIL KIM ,  Eun-Joo Lee ,  Christopher A. Spence

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical proximity correction (OPC) model including a plurality of terms is defined. Each term relates to at least one parameter in the optical profiles. A subset of the model terms is identified as being priority terms. Parameters of the optical profiles of the test features are matched to parameters of the optical profiles of the design target features using the priority terms to generate a set of matched test features. A metrology request is generated to collect metrology data from a test wafer having formed thereon at least a first subset of the matched test features and a second subset of the design target features.

    摘要翻译： 一种方法包括接收与集成电路设备相关联的多个设计目标特征的光学轮廓和用于多个测试特征的光学轮廓。 定义包括多个术语的光学邻近校正（OPC）模型。 每个术语涉及光学轮廓中的至少一个参数。 模型项的一个子集被确定为优先项。 使用优先级项将测试特征的光学轮廓的参数与设计目标特征的光学轮廓的参数匹配以生成一组匹配的测试特征。 产生计量学请求以从其上形成有至少匹配的测试特征的第一子集的测试晶片和设计目标特征的第二子集收集测量数据。

    Method of extending the areas of clear field phase shift generation
    25.
    发明授权
    Method of extending the areas of clear field phase shift generation 有权
    扩展清除场相移生成区域的方法

    公开(公告)号：US06818358B1

    公开(公告)日：2004-11-16

    申请号：US10016439

    申请日：2001-12-11

    申请人： Todd P. Lukanc ,  Christopher A. Spence

    发明人： Todd P. Lukanc ,  Christopher A. Spence

    IPC分类号： G03F900

    CPC分类号： G03F1/30

    摘要： An exemplary Full Phase patterning method involves patterning gates to increase process margins from conventional methods. This technique can define all poly patterns with a phase mask, using only a field or trim mask to resolve conflicts in the phase mask. The trim mask exposes a series of lines that either separates the different phase areas where patterns not desired or minimizes the range of sizes of the phase patterns next to a critical gate area.

    摘要翻译： 示例性的全相图案化方法包括图案化门以增加与常规方法的工艺裕度。 该技术可以使用相位掩模定义所有多边形图案，只使用字段或修剪蒙版来解决相位掩码中的冲突。 修剪掩模暴露一系列线，其中分离不期望的图案的不同相位区域，或者使关键栅极区域旁边的相位图案的尺寸范围最小化。

    Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion
    26.
    发明授权
    Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion 失效
    通过四维空间分析和/或小波变换扩展来表征和合成OPC结构

    公开(公告)号：US06492066B1

    公开(公告)日：2002-12-10

    申请号：US09321089

    申请日：1999-05-28

    申请人： Luigi Capodieci ,  Christopher A. Spence

    发明人： Luigi Capodieci ,  Christopher A. Spence

    IPC分类号： G03F900

    CPC分类号： G03F1/36

    摘要： A method (100) of characterizing optical proximity correction designs includes performing a mathematical transform (160) on a first feature (150) and a second feature (167) each having a core portion (152) and a first OPC design and a second OPC design applied thereto, respectively. The method (100) further includes obtaining a metric (162) for the transformed first and second features, wherein the metric is based upon a capability of a pattern transfer system which will utilize masks employing the first and second features (150, 167) as a patterns thereon. One of the first feature or the second feature is then selected (170) based upon an application of the metric to the first and second transformed features (150, 167), thereby selecting the one of the first feature or the second feature which provides for a better pattern transfer performance.

    摘要翻译： 表征光学邻近校正设计的方法（100）包括在第一特征（150）和第二特征（167）上执行数学变换（160）和第二特征（167），每个具有核心部分（152）和第一OPC设计和第二OPC 分别设计了其设计。 方法（100）还包括获得用于变换的第一和第二特征的度量（162），其中度量基于模式传送系统的能力，其将利用采用第一和第二特征（150,167）的掩模作为 其上的图案。 然后基于将度量应用于第一和第二变换特征（150,167）来选择第一特征或第二特征之一（170），从而选择第一特征或第二特征中的一个，其提供 更好的图案转移性能。

    Method for self-aligning polysilicon gates with field isolation and the resultant structure
    27.
    发明授权
    Method for self-aligning polysilicon gates with field isolation and the resultant structure 失效
    使用场隔离自对准多晶硅栅极的方法及其结果

    公开(公告)号：US6046088A

    公开(公告)日：2000-04-04

    申请号：US985400

    申请日：1997-12-05

    申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/6659

    摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

    摘要翻译： 在诸如浅​​氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面 多晶硅门 在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。 在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。 在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。

    Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
    28.
    发明授权
    Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin 有权
    通过考虑布局交互以及额外的可制造性边际来优化集成电路布局

    公开(公告)号：US07313769B1

    公开(公告)日：2007-12-25

    申请号：US10790381

    申请日：2004-03-01

    申请人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

    发明人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

    摘要翻译： 产生对应于集成电路（IC）设备设计的布局表示的方法可以包括根据预定的一组设计规则生成初始布局表示，并且模拟初始布局表示中的结构如何在晶片上进行图案化。 基于模拟，可以识别布局表示的部分，其包括展示不良可制造性的结构和/或其中存在额外的可制造裕度的布局表示的部分。 可以修改布局表示的部分，包括显示不良可制造性的结构和/或存在额外的可制造性裕度的部分，以优化布局表示。

    Method for evaluation of reticle image using aerial image simulator
    29.
    发明授权
    Method for evaluation of reticle image using aerial image simulator 有权
    使用航空图像模拟器评估光罩图像的方法

    公开(公告)号：US07120285B1

    公开(公告)日：2006-10-10

    申请号：US09515348

    申请日：2000-02-29

    申请人： Christopher A. Spence

    发明人： Christopher A. Spence

    IPC分类号： G06K9/46 ,  G06K9/68

    CPC分类号： G03F1/70

    摘要： A method of evaluating a wafer structure formation process includes extracting the outline of an actual mask pattern, and simulating a lithographic process using the actual mask pattern to obtain a simulated wafer structure. The extracting the outline of the actual mask pattern may include, for example, imaging the actual mask using a scanning electron microscope (SEM). A second simulated wafer structure may also be obtained, by simulating the lithographic process using the ideal mask pattern design that was used in producing the actual mask pattern. Thus the relative contribution of mask pattern effects to overall wafer proximity effects may be evaluated by comparing the two simulated wafer structures, either with each other or against a benchmark such as a desired, ideal structure. This information may then be used to generate optical proximity correction (OPC) mask designs which compensate for mask patterning errors and give better wafer performance. The simulated wafer structures may be overlaid upon one another to allow for a direct comparison and full analysis of CD variations.

    摘要翻译： 评估晶片结构形成处理的方法包括提取实际掩模图案的轮廓，并且使用实际掩模图案来模拟光刻处理以获得模拟的晶片结构。 提取实际掩模图案的轮廓可以包括例如使用扫描电子显微镜（SEM）对实际掩模进行成像。 也可以通过使用用于生产实际掩模图案的理想掩模图案设计来模拟光刻工艺来获得第二模拟晶片结构。 因此，掩模图案效应对整个晶片接近效应的相对贡献可以通过比较两个模拟晶片结构彼此或与诸如期望的理想结构之类的基准来评估。 然后可以使用该信息来产生补偿掩模图案化错误并提供更好的晶片性能的光学邻近校正（OPC）掩模设计。 模拟的晶片结构可以彼此重叠以允许CD变化的直接比较和全面分析。

    Reduce line end pull back by exposing and etching space after mask one trim and etch
    30.
    发明授权
    Reduce line end pull back by exposing and etching space after mask one trim and etch 有权
    通过在掩模一次修整和蚀刻后曝光和蚀刻空间来减少线端拉回

    公开(公告)号：US07015148B1

    公开(公告)日：2006-03-21

    申请号：US10852883

    申请日：2004-05-25

    申请人： Todd P. Lukanc ,  Luigi Capodieci ,  Christopher A. Spence ,  Joerg Reiss ,  Sarah N. McGowan

    发明人： Todd P. Lukanc ,  Luigi Capodieci ,  Christopher A. Spence ,  Joerg Reiss ,  Sarah N. McGowan

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/0276 ,  H01L21/28123 ,  H01L21/28282 ,  H01L21/32139

    摘要： The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension. The method includes the steps of: forming a photosensitive layer to be patterned, patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween, transferring the pattern to at least one underlying layer using the patterned photosensitive layer, forming a second photosensitive layer over the patterned at least one underlying layer, patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer, and transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension.

    摘要翻译： 本发明是制造半导体器件和这种半导体器件的方法。 半导体器件包括集成电路图案，其包括水平线，垂直线和它们之间的空间，该空间包括精确的宽度尺寸。 该方法包括以下步骤：形成待图案化的感光层，图案化感光层以形成包括主水平线和主垂直线的图案，其间没有间隙，使用图案化将图案转移到至少一个下层 在所述图案化的至少一个下层上形成第二感光层，对所述第二感光层进行图案化，以形成第二图案，所述第二图案包括对准以剖开在所述至少一个下层中形成的水​​平线和垂直线的主空间， 以及将所述第二图案转移到所述至少一个下层，以形成包括水平线和在其间具有空间的垂直线的第三图案，所述空间包括精确的宽度尺寸。