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公开(公告)号:US10938349B1
公开(公告)日:2021-03-02
申请号:US16692750
申请日:2019-11-22
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Niraja Shreekant Paranjape
Abstract: Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.
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公开(公告)号:US20200220567A1
公开(公告)日:2020-07-09
申请号:US16242870
申请日:2019-01-08
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Phanindra Yerramilli
Abstract: Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.
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公开(公告)号:US10700658B2
公开(公告)日:2020-06-30
申请号:US16029364
申请日:2018-07-06
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Ke Li , James Francis McElwee , Tero Tapio Ranta , Kevin Roberts , Chih-Chieh Cheng
IPC: H04B1/04 , H04B1/40 , H01B1/00 , H04W88/06 , H03H7/38 , H03H7/01 , H04B1/00 , H04W72/04 , H04W28/06 , H04L5/00
Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability. In a third version, CA direct mapped adaptive tuning networks include filter tuning blocks for selected lower frequency bands.
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公开(公告)号:US20250080070A1
公开(公告)日:2025-03-06
申请号:US18953752
申请日:2024-11-20
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Phanindra Yerramilli
Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
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公开(公告)号:US12184248B2
公开(公告)日:2024-12-31
申请号:US17741130
申请日:2022-05-10
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Phanindra Yerramilli
Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
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26.
公开(公告)号:US20240186958A1
公开(公告)日:2024-06-06
申请号:US18534153
申请日:2023-12-08
Applicant: pSemi Corporation
Inventor: Kashish Pal , Emre Ayranci , Miles Sanner
CPC classification number: H03F1/223 , H03F1/26 , H03F3/193 , H03F3/68 , H04L27/2647 , H03F1/0277 , H03F2200/294 , H03F2200/489
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号:US20240171145A1
公开(公告)日:2024-05-23
申请号:US18418147
申请日:2024-01-19
Applicant: pSemi Corporation
Inventor: Jing Li , Emre Ayranci , Miles Sanner
CPC classification number: H03G3/3036 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/72 , H03G1/0023 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03F2200/156 , H03F2200/159 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2200/61 , H03F2203/7239 , H03G3/3052 , H03G2201/504
Abstract: A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.
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公开(公告)号:US11705873B2
公开(公告)日:2023-07-18
申请号:US17965056
申请日:2022-10-13
Applicant: pSemi Corporation
Inventor: Miles Sanner , Emre Ayranci
IPC: H03F3/195 , H03F3/21 , H03F1/56 , H03F3/193 , H03F3/72 , H03F1/22 , H03F3/16 , H03F1/02 , H04B1/16
CPC classification number: H03F3/195 , H03F1/0211 , H03F1/223 , H03F1/56 , H03F3/16 , H03F3/193 , H03F3/211 , H03F3/72 , H03F2200/111 , H03F2200/222 , H03F2200/231 , H03F2200/249 , H03F2200/267 , H03F2200/294 , H03F2200/372 , H03F2200/387 , H03F2200/391 , H03F2200/396 , H03F2200/421 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2203/7209 , H04B1/16
Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
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公开(公告)号:US11606067B2
公开(公告)日:2023-03-14
申请号:US17189141
申请日:2021-03-01
Applicant: pSemi Corporation
Inventor: Miles Sanner , Emre Ayranci , Parvez Daruwalla
Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
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公开(公告)号:US20220231654A1
公开(公告)日:2022-07-21
申请号:US17669789
申请日:2022-02-11
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Ke Li , James Francis McElwee , Tero Tapio Ranta , Kevin Roberts , Chih-Chieh Cheng
Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability. In a third version, CA direct mapped adaptive tuning networks include filter tuning blocks for selected lower frequency bands.
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