公开(公告)号：US20200005980A1

公开(公告)日：2020-01-02

申请号：US16481600

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Congying DONG

IPC: H01F17/00 ,  H01L23/522

Abstract: A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.

公开(公告)号：US10466065B2

公开(公告)日：2019-11-05

申请号：US15321958

申请日：2015-06-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huagang Wu

IPC: G01C25/00 ,  G01C19/56 ,  G01C19/5776

Abstract: A method for correcting the driving amplitude of a gyro sensor, mainly comprises adjusting the size of a driving signal (a preset amplitude value) through feedback of a sensor response amplitude signal (an average amplitude value) in a resonance maintaining time period, so that the response amplitude of the resonance maintaining time period tends to be equal, and a stable resonance amplitude is maintained. Also provided is a system for correcting the driving amplitude of a gyro sensor.

公开(公告)号：US20190252537A1

公开(公告)日：2019-08-15

申请号：US16329413

申请日：2017-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Shikang CHENG ,  Sen ZHANG

IPC: H01L29/78 ,  H01L27/098 ,  H01L29/66

CPC classification number: H01L29/7803 ,  H01L27/02 ,  H01L27/06 ,  H01L27/098 ,  H01L29/06 ,  H01L29/66712

Abstract: A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain (201) having a first conduction type; and a first conduction type region (214) disposed on a front face of the drain; the JFET region further includes: a JFET source (208) having a first conduction type; a first well (202) having a second conduction type; a metal electrode (212) formed on the JFET source (208), which is in contact with the JFET source (208); a JFET metal gate (213) disposed on the first well (202) at both sides of the JFET source (208); and a first clamping region (210) located below the JFET metal gate (213) and within the first well (202).

公开(公告)号：US20190238122A1

公开(公告)日：2019-08-01

申请号：US16312345

申请日：2017-06-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Xueyan WANG ,  Qiang CHEN

IPC: H03K3/03 ,  H03K5/134 ,  H03L7/099 ,  H03B5/20

Abstract: A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.

公开(公告)号：US20190214983A1

公开(公告)日：2019-07-11

申请号：US16328402

申请日：2017-08-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chuan LUO

IPC: H03K17/687

CPC classification number: H03K17/6872 ,  H03K17/00

Abstract: A clock voltage step-up circuit comprises a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor. An input end of the first inverter is used for inputting a first clock signal. An input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter outputs a first control signal used for controlling a sampling switch; and after the first control signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch is generated. An input end of the third inverter is connected to a second clock signal, and the first clock signals and the second clock signals are a set of clock signals, every two of which are not overlapped. A gate end of the PMOS transistor is connected to a drain end of the PMOS transistor, and a source end of the PMOS transistor is used for being connected to a power supply. One end of the bootstrap capacitor is connected to an output end of the third inverter, and the other end of the bootstrap capacitor is connected to the drain end of the PMOS transistor and is connected to the second inverter, so as to step up a voltage of the first control signal.

公开(公告)号：US10290726B2

公开(公告)日：2019-05-14

申请号：US15548290

申请日：2016-01-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan Gu ,  Wei Su ,  Sen Zhang

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/735 ,  H01L29/739

Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).

公开(公告)号：US10290705B2

公开(公告)日：2019-05-14

申请号：US15564181

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Feng Huang ,  Guangtao Han ,  Guipeng Sun ,  Feng Lin ,  Longjie Zhao ,  Huatang Lin ,  Bing Zhao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/76 ,  H01L29/06 ,  H01L21/762

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).

公开(公告)号：US10199495B2

公开(公告)日：2019-02-05

申请号：US15766082

申请日：2016-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guipeng Sun

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.

公开(公告)号：US20180224281A1

公开(公告)日：2018-08-09

申请号：US15747882

申请日：2016-05-11

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huagang WU ,  Xueyan WANG

IPC: G01C19/5776 ,  G01P15/12 ,  G01P15/18

CPC classification number: G01C19/5776 ,  G01P15/0802 ,  G01P15/12 ,  G01P15/18 ,  G05B2219/36159

Abstract: An accelerator comprises: an accelerometer (100), configured to detect an acceleration of a motion of a carrier and output a corresponding electrical signal; a sampling and low-pass filter (200), coupled to the accelerometer (100), and configured to sample the electrical signal regularly and filter a noise from the electrical signal; an amplifier (300), configured to amplify the electrical signal after filtering the noise; an analog-to-digital converter (400), configured to convert the amplified electrical signal into a digital signal; a function control module (500), configured to process the digital signal and output a control signal to control the analog-to-digital converter (400), the amplifier (300), and the sampling and low-pass filter (200); and an oscillator module (600), configured to output, according to the control signal, a sampling signal to the sampling and low-pass filter (200), so as to control the sampling and low-pass filter (200) to sample the electrical signal regularly.

公开(公告)号：US09977342B2

公开(公告)日：2018-05-22

申请号：US15315168

申请日：2015-06-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zhenhai Yao

IPC: G03F9/00 ,  G03F7/20

CPC classification number: G03F7/70633 ,  G03F1/00 ,  G03F1/38 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7019 ,  G03F9/7046 ,  G03F9/7069

Abstract: A lithography stepper alignment and control method, comprising: providing a test template having a plurality of field sizes, and deriving a set of overlay values for each field size (S1); calculating a set of compensation amounts for the overlay value of each field size (S2); and, comparing a set of estimated alignment compensation values for a product with each compensation amount for each field size, selecting as the product alignment compensation values the set of compensation amounts of a field size closest to the set of estimated alignment compensation values, and, using the product alignment compensation values to perform alignment compensation on said product (S3).