公开(公告)号：US4567593A

公开(公告)日：1986-01-28

申请号：US539356

申请日：1983-10-06

Applicant: Lawrence D. Bashaw

Inventor： Lawrence D. Bashaw

IPC: G01R31/3185 ,  G06F11/273 ,  G06F11/00

CPC classification number: G01R31/318558 ,  G06F11/2294

Abstract: A specialized circuit set is included in a data processing system wherein the circuit set registers can be configured into a serial array. A clock signal distribution system delivers controlled clock signals to selected serial arrays. A maintenance data processor provides predetermined signal groups and addressing apparatus responsive to the predetermined signal groups loads and unloads register arrays in response to the predetermined signals. A predetermined signal group is entered into the serial register array, a predetermined number of clock cycles are applied, and the resulting signals shifted from the serial register array are applied to the maintenance data processor for display or analysis. By comparing the expected result for a given initial state with the actual result of an operation sequence, the accuracy of the operation of the data processing system, or any portion thereof, is thereby determined.

Abstract translation: 专用电路组包括在数据处理系统中，其中电路组寄存器可被配置成串行阵列。 时钟信号分配系统将受控的时钟信号传送到选定的串行阵列。 维护数据处理器响应于预定信号而提供响应于预定信号组加载和卸载寄存器阵列的预定信号组和寻址装置。 将预定的信号组输入到串行寄存器阵列中，施加预定数量的时钟周期，并将从串行寄存器阵列移位的结果信号应用于维护数据处理器进行显示或分析。 通过将给定初始状态的预期结果与操作序列的实际结果进行比较，由此确定数据处理系统或其任何部分的操作的精度。

公开(公告)号：US4561053A

公开(公告)日：1985-12-24

申请号：US560659

申请日：1983-12-12

Applicant: Knute S. Crawford

Inventor： Knute S. Crawford

IPC: G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F3/00

CPC classification number: G06F13/4022 ,  G06F11/22 ,  G06F13/12

Abstract: In an input/output multiplexer of a data processing unit, a plurality of components, capable of independent activity, provide for the simultaneous execution of a multiplicity of operations involving the exchange of signal groups between a central subsystem and peripheral subsystems. The input/output multiplexer includes apparatus for controlling the receipt from delivery to the central subsystem and peripheral subsystems of signal groups. Apparatus is provided to execute address development normally performed in the central subsystem. Apparatus is also provided to analyze control subsystem signal groups and generate pre-selected command signal groups for delivery to the central subsystem or to the peripheral subsystems. Apparatus in the input/output multiplexer also provides a status of each operation currently in execution.

Abstract translation: 在数据处理单元的输入/输出多路复用器中，能够独立运行的多个组件提供同时执行涉及中央子系统和外围子系统之间信号组交换的多种操作。 输入/输出多路复用器包括用于控制从传送到中央子系统和信号组的外围子系统的接收的装置。 提供设备来执行通常在中央子系统中执行的地址开发。 还提供了用于分析控制子系统信号组并生成用于传送到中央子系统或外围子系统的预选命令信号组的装置。 输入/输出多路复用器中的装置还提供当前执行的每个操作的状态。

公开(公告)号：US4558409A

公开(公告)日：1985-12-10

申请号：US669042

申请日：1984-11-06

Applicant: Gary J. Goss ,  Robert G. H. Moles ,  Randall D. Hinrichs

Inventor： Gary J. Goss ,  Robert G. H. Moles ,  Randall D. Hinrichs

IPC: H04L7/02 ,  H04L7/033 ,  H04L7/08

CPC classification number: H04L7/0066 ,  H04L7/0331

Abstract: An apparatus for decoding and synchronizing data wherein only logic ZERO data bits are received as electronic pulses, each pulse alternating in opposite directions and wherein logic ONE data bits are received as no pulse. The synchronization logic includes a counter which is delayed a count of binary ONE if the logic ZERO data bit is received late, and the counter is advanced a count of binary ONE if the logic ZERO data bit is received early.

Abstract translation: 一种用于解码和同步数据的装置，其中只有逻辑零数据位被接收为电子脉冲，每个脉冲以相反方向交替，并且其中逻辑1数据位被接收为无脉冲。 同步逻辑包括一个计数器，如果逻辑零数据位被接收到迟到，则该计数器被延迟二进制1的计数，并且如果提前接收到逻辑零数据位，则计数器提前二进制1的计数。

公开(公告)号：US4554598A

公开(公告)日：1985-11-19

申请号：US613936

申请日：1984-05-25

Applicant: Bruce H. Tarbox ,  Donald J. Rathbun ,  Taian Su

Inventor： Bruce H. Tarbox ,  Donald J. Rathbun ,  Taian Su

IPC: G06F3/06 ,  G11B20/12 ,  G11B5/09

CPC classification number: G06F3/0607 ,  G06F3/064 ,  G06F3/0676 ,  G11B20/1252 ,  G11B2220/2508

Abstract: A track of a disk device is formatted on a single revolution of the disk by using a read only memory (ROM) to store control codes and a random access memory (RAM) to store address field and data field bytes. A DMA controller simultaneously addresses ROM and RAM. Control codes are read into a control first in-first out memory and data codes are read into a data first in-first out memory. The control codes are applied to a decoder whose output signals control cyclic redundancy check and error detection and correction logic as well as the data first in-first out memory. The serial output from both the data first in-first out memory and the cyclic redundancy check logic are written on disk track.

Abstract translation: 通过使用只读存储器（ROM）来存储控制代码和磁盘存储器（RAM）来存储地址字段和数据字段字节，磁盘设备的轨道在盘的一圈上被格式化。 DMA控制器同时处理ROM和RAM。 将控制代码读入控制先进先出存储器，并将数据代码读入数据先进先出存储器。 控制码被应用于其输出信号控制循环冗余校验和错误检测和校正逻辑以及数据先进先出存储器的解码器。 数据先进先出存储器和循环冗余校验逻辑的串行输出都写在磁盘轨上。

公开(公告)号：US4554445A

公开(公告)日：1985-11-19

申请号：US607836

申请日：1984-05-07

Applicant: Dennis W. Chasse ,  Vincent M. Clark

Inventor： Dennis W. Chasse ,  Vincent M. Clark

IPC: G06K7/016 ,  G06K7/08 ,  H03K5/05 ,  G06K7/10

CPC classification number: H03K5/05 ,  G06K7/016 ,  G06K7/089

Abstract: An apparatus for varying the pulse width of a computer clock by adding a predetermined amount of time to the clock pulse width. A synchronous counter is combined with a latch into a circuit whereby a pulse input to the circuit resets both the latch and counter on the leading edge, and whereby the trailing edge of the input pulse releases the latch and counter allowing the counter to count clock pulses. On a predetermined pulse the counter's carry-output terminal clocks a logic high into the D latch terminal. Concurrently, an output from the latch is fed back to the counter's count-enable input to disable counting until a subsequent pulse resets the circuit. The net effect is to add a predetermined amount of time to the input pulse so that the extended pulse is available at the output of the latch.

Abstract translation: 一种用于通过向时钟脉冲宽度添加预定量的时间来改变计算机时钟的脉冲宽度的装置。 同步计数器与锁存器组合成电路，由此输入到电路的脉冲在前沿复位锁存器和计数器，由此输入脉冲的后沿释放锁存器和计数器，允许计数器对时钟脉冲进行计数 。 在预定脉冲上，计数器的进位输出端将逻辑高电平时钟锁定到D锁存器端。 同时，锁存器的输出反馈到计数器的计数使能输入，以禁止计数，直到后续脉冲复位电路。 净效果是向输入脉冲添加预定量的时间，使得扩展脉冲在锁存器的输出处可用。

公开(公告)号：US4542517A

公开(公告)日：1985-09-17

申请号：US304755

申请日：1981-09-23

Applicant: Gary J. Goss ,  Robert G. H. Moles ,  Randall D. Hinrichs ,  Thomas O. Holtey

Inventor： Gary J. Goss ,  Robert G. H. Moles ,  Randall D. Hinrichs ,  Thomas O. Holtey

IPC: G06F13/42 ,  H04L7/02 ,  H04L7/033 ,  H04L25/49

CPC classification number: H04L7/0066 ,  G06F13/4221 ,  H04L25/4925 ,  H04L7/0331

Abstract: An apparatus for encoding data for serial transmission wherein only logic ZEROs are transmitted as electronic pulses, each pulse alternating in opposite direction and wherein logic ONEs require no pulse.

Abstract translation: 一种用于串行传输的数据编码装置，其中只有逻辑ZERO作为电子脉冲发送，每个脉冲以相反方向交替，其中逻辑1不需要脉冲。

公开(公告)号：USD280198S

公开(公告)日：1985-08-20

申请号：US468915

申请日：1983-02-23

Applicant: Richard R. Dillon ,  David G. Kmetz ,  Edward J. Cesarczyk

Designer： Richard R. Dillon ,  David G. Kmetz ,  Edward J. Cesarczyk

公开(公告)号：US4535330A

公开(公告)日：1985-08-13

申请号：US372907

申请日：1982-04-29

Applicant: Richard A. Carey ,  Jerry Falk

Inventor： Richard A. Carey ,  Jerry Falk

IPC: G06F13/30 ,  G06F13/364 ,  G06F9/00 ,  H04Q9/00

CPC classification number: G06F13/364 ,  G06F13/30

Abstract: An interactive computer terminal system having a bus for communication between elements of the system is disclosed having apparatus for assigning control of the computer bus on a predetermined order of priority. The CPU receives requests from computer system elements and assigns time slots for use of the system bus by arbitrating among various resources competing for access to the bus.

Abstract translation: 公开了具有用于在系统的元件之间进行通信的总线的交互式计算机终端系统，具有以预定优先顺序分配计算机总线的控制的装置。 CPU从计算机系统元件接收请求，并通过在竞争访问总线的各种资源之间进行仲裁来分配使用系统总线的时隙。

公开(公告)号：US4534044A

公开(公告)日：1985-08-06

申请号：US490613

申请日：1983-05-02

Applicant: Michael J. Funke ,  Douglas A. Topliffe ,  Donald J. Rathbun

Inventor： Michael J. Funke ,  Douglas A. Topliffe ,  Donald J. Rathbun

IPC: G11B20/14 ,  H03L7/089 ,  H03L7/183 ,  H03L7/06 ,  G11B5/09

CPC classification number: H03L7/0891 ,  G11B20/1419 ,  G11B20/1423 ,  H03L7/183

Abstract: A diskette read data recovery system generates a clock which is locked to an incoming data stream. In a phase locked loop, a signal generated by an oscillator and frequency dividers is compared in phase to the incoming data stream to provide first or second signals depending on whether the incoming data signal leads or lags the clock signal. In order that the system may handle different types of incoming signals, different frequency divider circuits in the phase locked loop are selected for different incoming signals.

Abstract translation: 磁盘读取数据恢复系统生成锁定到输入数据流的时钟。 在锁相环中，由振荡器和分频器产生的信号与输入数据流进行相位比较，以根据输入的数据信号是导通还是滞后于时钟信号来提供第一或第二信号。 为了使系统可以处理不同类型的输入信号，针对不同的输入信号选择锁相环中的不同分频器电路。

公开(公告)号：US4530052A

公开(公告)日：1985-07-16

申请号：US434383

申请日：1982-10-14

Applicant: James L. King ,  Marion G. Porter ,  Phillip A. Angelle ,  Joseph C. Circello ,  John E. Wilhite ,  Leonard G. Trubisky

Inventor： James L. King ,  Marion G. Porter ,  Phillip A. Angelle ,  Joseph C. Circello ,  John E. Wilhite ,  Leonard G. Trubisky

IPC: G06F12/10 ,  G06F9/455 ,  G06F9/46 ,  G06F12/14 ,  G06F9/00

CPC classification number: G06F9/45537

Abstract: Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserved memory area associated with the currently active operating system is then addressed and register contents of a central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory and, data establishing the decor of the operating system being activated are entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun. The physical memory locations are determined by a real address through use of a paging mechanism permitting storage of portions of the operating systems in non-contiguous groups of locations while isolating the memory available to each operating system.

Abstract translation: 一种用于能够利用多个操作系统的数据处理系统的主管的装置和方法。 主管包括用于识别需要不同操作系统的数据处理系统中的状况的装置。 然后寻址与当前活动的操作系统相关联的保留存储器区域，并且将中央处理单元的寄存器内容存储在保留的存储器区域中。 正在激活的操作系统的预留存储器被寻址，并且使得操作系统的保留存储器的地址被激活，与允许与操作系统相关联的物理存储器被激活的数据，保存在存储器中的寄存器的内容， 存储器和建立被激活的操作系统的装饰的数据被输入到中央处理单元中。 然后启用要激活的操作系统，并且开始由第二操作系统执行允许的指令。 通过使用分页机制来确定物理存储器位置，该分页机制允许在不连续的位置组中存储部分操作系统，同时隔离每个操作系统可用的存储器。