公开(公告)号：US20090057640A1

公开(公告)日：2009-03-05

申请号：US11964496

申请日：2007-12-26

Applicant: Yung-Fa Lin ,  Yen-Wen Wang

Inventor： Yung-Fa Lin ,  Yen-Wen Wang

IPC: H01L47/00

CPC classification number: H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144

Abstract: A phase-change memory element and fabrication method thereof is provided. The phase-change memory element comprises an electrode. A first dielectric layer is formed on the substrate. An opening passes through the first dielectric layer exposing the electrode. A heater with an extended part is formed in the opening, wherein the extended part protrudes the opening. A second dielectric layer surrounds the extended part of the heater exposing the top surface of the extended part. A phase-changed material layer is formed on the second dielectric layer to directly contact the top of the extended part.

Abstract translation: 提供了相变存储元件及其制造方法。 相变存储元件包括电极。 在基板上形成第一电介质层。 开口穿过暴露电极的第一电介质层。 具有延伸部分的加热器形成在开口中，其中延伸部分突出开口。 第二电介质层围绕加热器的延伸部分暴露延伸部分的顶表面。 在第二电介质层上形成相变材料层，以直接接触延伸部分的顶部。

公开(公告)号：US20090053870A1

公开(公告)日：2009-02-26

申请号：US12031653

申请日：2008-02-14

Applicant: CHUNG WE PAN ,  TZENG WEN TZENG ,  MING YU HO ,  YEN YU HSU ,  CHIH PING CHUNG ,  CHING HUNG FU

Inventor： CHUNG WE PAN ,  TZENG WEN TZENG ,  MING YU HO ,  YEN YU HSU ,  CHIH PING CHUNG ,  CHING HUNG FU

IPC: H01L21/8239

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/792

Abstract: A method for preparing a flash memory structure comprises the steps of forming a plurality of dielectric blocks having block sidewalls on a substrate, forming a plurality of first spacers on the block sidewalls of the dielectric blocks, removing a portion of the substrate not covered by the dielectric blocks and the first spacers to form a plurality of trenches in the substrate, performing a deposition process to form an isolation dielectric layer filling the trenches, removing the dielectric blocks to expose spacer sidewalls of the first spacers, forming a plurality of second spacers on the spacer sidewalls of the first spacers, and removing a portion of the substrate not covered by the first spacers, the second spacers and the isolation dielectric layer to form a plurality of second trenches in the substrate.

Abstract translation: 一种制备闪速存储器结构的方法包括以下步骤：在衬底上形成具有块侧壁的多个介质块，在介质块的块侧壁上形成多个第一间隔物，去除未覆盖的衬底的一部分 介质块和第一间隔物，以在衬底中形成多个沟槽，执行沉积工艺以形成填充沟槽的隔离电介质层，去除介质块以暴露第一间隔物的间隔壁侧壁，形成多个第二隔离物 所述第一间隔件的间隔件侧壁，以及去除未被所述第一间隔件，所述第二间隔件和所述隔离介电层覆盖的所述基板的一部分，以在所述基板中形成多个第二沟槽。

公开(公告)号：US20090045386A1

公开(公告)日：2009-02-19

申请号：US11889522

申请日：2007-08-14

Applicant: Frederick T. Chen

Inventor： Frederick T. Chen

IPC: H01L45/00 ,  G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C2213/56 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase-change memory element. The phase-change memory element comprises a first electrode and a second electrode. A first phase change layer is electrically coupled to the first electrode. A second phase change layer is electrically coupled to the second electrode. A conductive bridge is formed between and electrically coupled to the first and second phase change layers.

Abstract translation: 相变存储元件。 相变存储元件包括第一电极和第二电极。 第一相变层电耦合到第一电极。 第二相变层电耦合到第二电极。 导电桥形成在电耦合到第一和第二相变层之间。

公开(公告)号：US20090023264A1

公开(公告)日：2009-01-22

申请号：US12050649

申请日：2008-03-18

Applicant: Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

Inventor： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC: H01L21/02

CPC classification number: H01L28/91

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract translation: 公开了制造半导体器件的平面型底电极的方法。 在基板上形成牺牲层结构。 在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。 第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。 多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。 第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。 绝缘层分别分开彼此分离的底部电极层。 最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

公开(公告)号：US07479452B2

公开(公告)日：2009-01-20

申请号：US11104213

申请日：2005-04-12

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L21/44

CPC classification number: H01L21/76877 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76897 ,  H01L27/10885 ,  H01L27/10894

Abstract: A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.

Abstract translation: 在本发明中公开了一种形成电池位线接触插塞的方法。 在提供具有第一区域和第二区域的半导体衬底之后，在第一区域形成单元位线触点。 在第二区域形成位线图形开口之后，在单元位线触点和位线图形开口的侧壁上形成多个间隔物。 然后在第二区域的开口内形成衬底接触和栅极接触。 通过进行蚀刻工艺在每个基板接触和栅极接触之间形成沟槽之后，形成电池 - 位线接触插塞，基板接触插塞和栅极接触插头。

公开(公告)号：US20090014834A1

公开(公告)日：2009-01-15

申请号：US12216146

申请日：2008-06-30

Applicant: Hsueh Yi Che

Inventor： Hsueh Yi Che

IPC: H01L29/92

CPC classification number: H01L27/10888

Abstract: A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with respect to the contact plug structure via a doped region isolated by a shallow trench isolation structure. Preferably, the body portion and the two leg portions can be made of the same conductive material selected from the group consisting of polysilicon, doped polysilicon, tungsten, copper and aluminum, while the dielectric block can be made of material selected from the group consisting of borophosphosilicate glass. Particularly, the contact plug can be prepared by dual-damascene technique. Since the overlapped area between the contact plug structure and a word line can be dramatically decreased, the bit line coupling (BLC) can be effectively reduced.

Abstract translation: 用于棋盘动态随机存取存储器的接触插头结构包括主体部分，连接到主体部分的两个腿部部分和位于两个腿部之间的介质块。 每个支脚部分经由由浅沟槽隔离结构隔离的掺杂区域相对于接触插塞结构电连接到以S形方式设置的深沟槽电容器。 优选地，主体部分和两个腿部分可以由选自多晶硅，掺杂多晶硅，钨，铜和铝的相同的导电材料制成，而介电块可以由选自以下的材料制成： 硼磷硅酸盐玻璃。 特别地，接触插塞可以通过双镶嵌技术制备。 由于可以显着地减小接触插塞结构和字线之间的重叠区域，所以可以有效地减少位线耦合（BLC）。

公开(公告)号：US20090011561A1

公开(公告)日：2009-01-08

申请号：US11902314

申请日：2007-09-20

Applicant: Min-Liang Chen

Inventor： Min-Liang Chen

IPC: H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating high-voltage MOS having double-diffused drain (DDD) is disclosed. The original photoresist used to define a gate is used to define double-diffused drains without increasing the complexity of the whole process. A dielectric layer and a conductive layer are sequentially formed on a substrate. A patterned photoresist is then formed on the conductive layer and then used to etch the conductive layer and the dielectric layer to form a gate and a gate dielectric layer, respectively. After stabilizing the photoresist layer, a first ion implantation is performed to form lightly doped region having deep junction. The photoresist is removed and two spacers are formed on the sidewalls of the gate. Next, a second ion implantation is performed to form heavily doped region in the substrate on outer side of the spacers.

Abstract translation: 公开了制造具有双扩散漏极（DDD）的高压MOS的方法。 用于限定栅极的原始光刻胶用于定义双扩散排水管，而不会增加整个过程的复杂性。 介电层和导电层依次形成在基板上。 然后在导电层上形成图案化的光致抗蚀剂，然后分别用于蚀刻导电层和电介质层以形成栅极和栅极电介质层。 在稳定光致抗蚀剂层之后，进行第一离子注入以形成具有深结的轻掺杂区域。 去除光致抗蚀剂，并且在栅极的侧壁上形成两个间隔物。 接下来，进行第二离子注入以在衬垫的外侧上形成重掺杂区域。

公开(公告)号：US20080290335A1

公开(公告)日：2008-11-27

申请号：US11940563

申请日：2007-11-15

Applicant: Yung-Fa Lin ,  Te-Chun Wang

Inventor： Yung-Fa Lin ,  Te-Chun Wang

IPC: H01L47/00

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691 ,  Y10S438/90

Abstract: A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers.

Abstract translation: 一种相变存储器件，包括衬底。 彼此隔离的多个底部电极在基板上。 绝缘层与相邻的两个底部电极的表面的一部分交叉。 一对相变材料间隔物位于绝缘层的一对侧壁上，其中一对相变材料间隔物分别位于相邻的两个底部电极之间。 顶部电极位于绝缘层上并覆盖相变材料间隔物。

公开(公告)号：US07456458B2

公开(公告)日：2008-11-25

申请号：US11402871

申请日：2006-04-13

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L27/108

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Abstract translation: 具有垂直浮体单元的动态随机存取存储器结构包括具有多个圆柱形柱状物的半导体衬底，位于圆柱形柱体顶部的上部导电区域，位于圆柱形柱体中的上部导电部分下方的主体， 位于圆柱形柱体的主体下方的底部导电部分，围绕圆柱形柱的侧壁的栅极氧化物层和围绕栅极氧化物层的栅极结构。 上导电区域用作漏电极，底部导电区域用作源电极，并且主体可以存储诸如孔的载体。 优选地，动态随机存取存储器结构还包括位于半导体衬底的表面上的导电层，以电连接圆柱形支柱中的底部导电区域。

公开(公告)号：US20080242096A1

公开(公告)日：2008-10-02

申请号：US11776793

申请日：2007-07-12

Applicant: Heng Kai Hsu

Inventor： Heng Kai Hsu

IPC: H01L21/311

CPC classification number: H01L29/66181 ,  H01L27/1087

Abstract: A method for preparing a bottle-shaped deep trench first forms a first mask with at least one opening on a substrate including a first epitaxy layer, an insulation layer on the first epitaxy layer and a second epitaxy layer on the insulation layer. A first etching process is performed to remove a portion of the substrate under the opening down to the interior of the insulation layer to form a trench, and a thermal treating process is then performed to form a second mask on the inner sidewall of the trench. Subsequently, a second etching process is performed to remove a portion of the substrate under the opening down to the interior of the first epitaxy layer to form a deep trench, and a third etching process is performed to remove a portion of the first epitaxy layer so as to form the bottle-shaped deep trench with an enlarged surface.

Abstract translation: 首先制备瓶形深沟槽的方法首先在基板上形成具有至少一个开口的第一掩模，该第一掩模包括第一外延层，第一外延层上的绝缘层和绝缘层上的第二外延层。 执行第一蚀刻工艺，以将开口下方的衬底的一部分向下移动到绝缘层的内部以形成沟槽，然后执行热处理工艺以在沟槽的内侧壁上形成第二掩模。 随后，进行第二蚀刻工艺，以将开口下的衬底的一部分向下移动到第一外延层的内部以形成深沟槽，并且执行第三蚀刻工艺以去除第一外延层的一部分，从而 以形成具有扩大表面的瓶形深沟槽。