公开(公告)号：US20230164928A1

公开(公告)日：2023-05-25

申请号：US17945106

申请日：2022-09-15

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Ta Ko ,  Pu-Ju Lin ,  Shih-Chieh Chen ,  Chi-Hai Kuo ,  Jeng-Ting Li

IPC: H05K3/46 ,  H05K1/03 ,  H05K1/11 ,  H05K3/06

CPC classification number: H05K3/4691 ,  H05K1/0393 ,  H05K1/118 ,  H05K3/06 ,  H05K2201/0154 ,  H05K2201/09509

Abstract: A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

公开(公告)号：US20230163074A1

公开(公告)日：2023-05-25

申请号：US17569509

申请日：2022-01-06

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/532 ,  H01L23/495 ,  H01L23/538

CPC classification number: H01L23/5329 ,  H01L23/53238 ,  H01L23/49503 ,  H01L23/5389

Abstract: A chip packaging structure and a manufacturing method thereof are provided. The chip packaging structure includes a substrate, at least one first chip, an adhesive material, a redistribution circuit structure, and multiple second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one cavity. The at least one first chip is disposed in the at least one cavity. The adhesive material is disposed in the at least one cavity and located between the substrate and the at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate, and is electrically connected to the at least one first chip. The second chips are disposed on the redistribution circuit structure, and are electrically connected to the redistribution circuit structure.

公开(公告)号：US20230156909A1

公开(公告)日：2023-05-18

申请号：US17873153

申请日：2022-07-26

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K1/02

CPC classification number: H05K1/0222 ,  H05K1/024 ,  H05K2201/09536 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096

Abstract: A circuit board structure includes a first dielectric layer, first and second inner circuit layers, a conductive connection layer, a second dielectric layer, two third dielectric layers, third and fourth inner circuit layers, two conductive through vias, first and second annular retaining walls, two fourth dielectric layers, first and second external circuit layers, and third and fourth annular retaining walls. The conductive through vias penetrate the third and second dielectric layers and electrically connect the third and fourth inner circuit layers. The first and second annular retaining walls surround the conductive through vias and electrically connect the third and first and the fourth and second inner circuit layers. The third and fourth annular retaining walls are respectively disposed in the fourth dielectric layers and electrically connect the first external circuit layer and the third inner circuit layer and the second external circuit layer and the fourth inner circuit layer.

公开(公告)号：US11637047B2

公开(公告)日：2023-04-25

申请号：US17875443

申请日：2022-07-28

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/78

Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.

公开(公告)号：US11579178B1

公开(公告)日：2023-02-14

申请号：US17647012

申请日：2022-01-04

Applicant: Unimicron Technology Corp.

Inventor： Hsin-Hung Lee ,  Chun-Hsien Chien ,  Yu-Chung Hsieh ,  Yi-Hsiu Fang ,  Tzyy-Jang Tseng

IPC: G01R29/08

Abstract: An inspection apparatus used for inspecting a bare circuit board is provided, where the bare circuit board includes an antenna. The inspection apparatus includes a holding stage, a probing device, and a measurement device. The holding stage can hold the bare circuit board. The measurement device is electrically connected to the probing device and electrically connected to the antenna via the probing device. The measurement device can input a first testing signal to the antenna. The antenna can input a second testing signal to the measurement device after receiving the first testing signal. The measurement device can measure the antenna according to the second testing signal, where the first testing signal and the second testing signal both pass through no active component.

公开(公告)号：US20220408547A1

公开(公告)日：2022-12-22

申请号：US17896053

申请日：2022-08-25

Applicant: Unimicron Technology Corp.

Inventor： Yu-Shen Chen

IPC: H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367

Abstract: A method for manufacturing an embedded component structure includes providing a circuit board having a through hole and a heat dissipation layer; disposing a chip in the through hole; forming a dielectric layer on a first surface and a second surface of the circuit board to seal the chip and cover a lower surface of the heat dissipation layer; removing a first part of the dielectric layer to form a first opening from which a upper surface of the heat dissipation layer is exposed and a second opening from which the lower surface of the heat dissipation layer is exposed; and forming a thermal conductive material layer in the first and the second opening to form a heat dissipation element surrounding the chip. The upper surface of the heat dissipation layer is exposed from the through hole. The chip, the circuit board, and the heat dissipation element are electrically connected.

公开(公告)号：US11523505B2

公开(公告)日：2022-12-06

申请号：US17406115

申请日：2021-08-19

Applicant: Unimicron Technology Corp.

Inventor： Yu-Shen Chen ,  I-Ta Tsai ,  Chien-Chih Chen

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46

Abstract: An embedded component structure includes a circuit board, an electronic component, a first conductive terminal, and a second conductive terminal. The circuit board includes a first electrical connection layer and a second electrical connection layer. The electronic component is embedded in the circuit board and includes a first contact and a second contact. The first conductive terminal and the second conductive terminal respectively at least cover a part of top surfaces and side walls of the first contact and the second contact, and the first electrical connection layer and the second electrical connection layer are respectively electrically connected to the first contact and the second contact through the first conductive terminal and the second conductive terminal. A method for manufacturing an embedded component structure is also provided.

公开(公告)号：US20220344248A1

公开(公告)日：2022-10-27

申请号：US17235944

申请日：2021-04-21

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chi-Hai Kuo ,  Chia-Yu Peng ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

公开(公告)号：US11483925B2

公开(公告)日：2022-10-25

申请号：US17185216

申请日：2021-02-25

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Chun Hung Kuo ,  Kuo Ching Chen

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/20

Abstract: A circuit board is manufactured by mounting a first circuit layer, mounting a conductive bump on the first circuit layer, covering the first circuit layer with a first dielectric layer which exposes the conductive bump, mounting a second dielectric layer on the first dielectric layer with a second dielectric layer opening that exposes the conductive bump, and finally, mounting a second circuit layer on the surface of the second dielectric layer and in the second dielectric layer opening. Since the surface roughness of the second dielectric layer and the second dielectric layer opening is low, it is unlikely to form nano voids between the second dielectric layer and the second circuit layer, and the second circuit layer may be attached to the second dielectric layer firmly, which is an advantage for fine line circuit disposal.

公开(公告)号：US11424216B2

公开(公告)日：2022-08-23

申请号：US17030380

申请日：2020-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chia-Fu Hsu ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/48 ,  H01L23/00

Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.