公开(公告)号：US09825593B2

公开(公告)日：2017-11-21

申请号：US15071350

申请日：2016-03-16

申请人： Technische Universiteit Delft

发明人： Leonardus C. N. de Vreede ,  Earl W. McCune, Jr.

IPC分类号： H03F1/02 ,  H03F3/19 ,  H03F3/21

CPC分类号： H03F1/0288 ,  H03F1/025 ,  H03F1/0277 ,  H03F3/19 ,  H03F3/21 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/102 ,  H03F2200/321 ,  H03F2200/36 ,  H03F2200/451 ,  H03F2200/516 ,  H03F2203/21106 ,  H03F2203/21109 ,  H03F2203/21131 ,  H03F2203/21142 ,  H03F2203/21145 ,  H03F2203/21154 ,  H03F2203/7236

摘要： A radio frequency power amplifier (RF PA) apparatus includes a first RF PA, a second RF PA, and a controller. The first RF PA is configured to deliver RF power to a load over a first range of RF power levels. The second RF PA is configured to deliver RF power to the load over a second range of RF power levels greater than the first range of RF power levels. The controller controls whether the first RF PA is delivering RF power to the load or the second RF PA is delivering RF power to the load, and is further configured to coordinate and control handoffs between the first and second RF PAs by varying magnitudes of input RF voltages applied to the RF input ports of the first and second RF PAs or by varying magnitudes of input bias voltages applied to the RF input ports of the first and second RF PAs.

公开(公告)号：US09698785B2

公开(公告)日：2017-07-04

申请号：US15255159

申请日：2016-09-02

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

公开(公告)号：US20140348264A1

公开(公告)日：2014-11-27

申请号：US14281902

申请日：2014-05-20

申请人： MEDIATEK INC.

发明人： Wen-Chieh Wang ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  I-Wen Liu ,  Khurram Muhammad ,  Chih-Ming Hung

IPC分类号： H04B1/04 ,  H04L25/08 ,  H04L25/02

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

摘要翻译： 数字发射机包括：多个可调延迟线，其布置成通过多个延迟时间来延迟多个数字输入信号，以分别产生多个延迟的数字输入信号; 多个转换装置，被配置为分别将多个延迟的数字输入信号转换成多个转换信号; 以及校准装置，其布置成调整多个可调延迟线中的至少一个可调节延迟线的延迟时间，以使多个转换装置在相应的期望时间点转换多个延迟的数字输入信号。

公开(公告)号：US20140347127A1

公开(公告)日：2014-11-27

申请号：US14267929

申请日：2014-05-02

申请人： Mediatek Inc.

发明人： Yang-Chuan Chen ,  Hsiang-Hui Chang

IPC分类号： H03F3/217

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

摘要翻译： 开关功率放大器包括：由第一数字信号控制的第一晶体管，以选择性地输出第一输出信号; 由第二数字信号控制的第二晶体管，以选择性地输出第二输出信号; 以及控制电路，被配置为根据第一数字信号和第三数字信号产生第二数字信号; 其中所述第一输出信号和所述第二输出信号在所述第一晶体管和所述第二晶体管的公共连接的节点上输出。

公开(公告)号：US07348849B2

公开(公告)日：2008-03-25

申请号：US11497461

申请日：2006-08-01

申请人： Seon Ho Han ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Hyun Kyu Yu

IPC分类号： H03F3/45 ,  H03G3/10

CPC分类号： H03G1/007 ,  H03F1/342 ,  H03F3/211 ,  H03F3/45206 ,  H03F3/45659 ,  H03F2200/15 ,  H03F2203/21154 ,  H03F2203/45008 ,  H03F2203/45302 ,  H03G7/06

摘要： A complementary metal oxide semiconductor (CMOS) variable gain amplifier has a wider decibel-linear gain variation characteristic with respect to a control voltage when a signal is amplified. The variable gain amplifier includes: a bias input circuit for supplying a current corresponding to a bias voltage; an operation region combination and feedback circuit connected to the bias input circuit and combining at least two amplifiers by feedback in response to a control voltage, each amplifier having a decibel-linear characteristic in saturation and triode regions of a complementary metal oxide semiconductor (CMOS); and a bias output circuit connected to the bias input circuit, and outputting bias current controlled by the operation region combination and feedback circuit.

摘要翻译： 互补金属氧化物半导体（CMOS）可变增益放大器在信号被放大时相对于控制电压具有更宽的分贝线性增益变化特性。 可变增益放大器包括：偏置输入电路，用于提供对应于偏置电压的电流; 连接到偏置输入电路的操作区域组合和反馈电路，并且通过响应于控制电压的反馈来组合至少两个放大器，每个放大器在互补金属氧化物半导体（CMOS）的饱和度和三极管区域中具有分贝线性特性， ; 以及偏置输出电路，连接到偏置输入电路，并输出由操作区域组合和反馈电路控制的偏置电流。

公开(公告)号：US20070132513A1

公开(公告)日：2007-06-14

申请号：US11497461

申请日：2006-08-01

申请人： Seon Ho Han ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Hyun Kyu Yu

IPC分类号： H03G3/10

CPC分类号： H03G1/007 ,  H03F1/342 ,  H03F3/211 ,  H03F3/45206 ,  H03F3/45659 ,  H03F2200/15 ,  H03F2203/21154 ,  H03F2203/45008 ,  H03F2203/45302 ,  H03G7/06

摘要： A complementary metal oxide semiconductor (CMOS) variable gain amplifier has a wider decibel-linear gain variation characteristic with respect to a control voltage when a signal is amplified. The variable gain amplifier includes: a bias input circuit for supplying a current corresponding to a bias voltage; an operation region combination and feedback circuit connected to the bias input circuit and combining at least two amplifiers by feedback in response to a control voltage, each amplifier having a decibel-linear characteristic in saturation and triode regions of a complementary metal oxide semiconductor (CMOS); and a bias output circuit connected to the bias input circuit, and outputting bias current controlled by the operation region combination and feedback circuit.

摘要翻译： 互补金属氧化物半导体（CMOS）可变增益放大器在信号被放大时相对于控制电压具有更宽的分贝线性增益变化特性。 可变增益放大器包括：偏置输入电路，用于提供对应于偏置电压的电流; 连接到偏置输入电路的操作区域组合和反馈电路，并且通过响应于控制电压的反馈来组合至少两个放大器，每个放大器在互补金属氧化物半导体（CMOS）的饱和度和三极管区域中具有分贝线性特性， ; 以及偏置输出电路，连接到偏置输入电路，并输出由操作区域组合和反馈电路控制的偏置电流。