公开(公告)号：US20110089970A1

公开(公告)日：2011-04-21

申请号：US12676892

申请日：2008-09-08

申请人： Trevis Chandler ,  Jason Redgrave ,  Martin Voogel

发明人： Trevis Chandler ,  Jason Redgrave ,  Martin Voogel

IPC分类号： H03K19/173

CPC分类号： H03K19/0008 ,  G06F15/7867 ,  G11C7/1045 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K3/0372 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17768 ,  H01L2924/00 ,  H01L2924/00014

摘要： Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

摘要翻译： 一些实施例向IC提供配置上下文切换器。 IC包括几个可配置电路，每个可配置电路可以在任何给定时间根据当时接收到的配置数据集配置执行多个操作之一。 IC包括多个存储电路，用于存储每个可配置电路的几个配置数据组。 IC还包括用于将可配置电路可切换地连接到不同组的存储电路以接收不同组的配置数据集的上下文切换互连电路。 上下文切换器包括用于重新定时来自配置存储元件的数据的一个或多个阶段。 这些阶段可以包括互连电路或存储电路。 一些实施例构建配置数据存储元件中的一个阶段。 一些实施例对配置数据位进行编码，并因此利用上下文切换器中的解码器对编码的配置数据进行解码。

公开(公告)号：US07928761B2

公开(公告)日：2011-04-19

申请号：US12206718

申请日：2008-09-08

申请人： Martin Voogel ,  Jason Redgrave ,  Trevis Chandler

发明人： Martin Voogel ,  Jason Redgrave ,  Trevis Chandler

IPC分类号： H03K19/173 ,  H03K17/693

CPC分类号： H03K19/0008 ,  G06F15/7867 ,  G11C7/1045 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K3/0372 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17768 ,  H01L2924/00 ,  H01L2924/00014

摘要： Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

摘要翻译： 一些实施例向IC提供配置上下文切换器。 IC包括几个可配置电路，每个可配置电路可以在任何给定时间根据当时接收到的配置数据集配置执行多个操作之一。 IC包括多个存储电路，用于存储每个可配置电路的几个配置数据组。 IC还包括用于将可配置电路可切换地连接到不同组的存储电路以接收不同组的配置数据集的上下文切换互连电路。 上下文切换器包括用于重新定时来自配置存储元件的数据的一个或多个阶段。 这些阶段可以包括互连电路或存储电路。 一些实施例构建配置数据存储元件中的一个阶段。 一些实施例对配置数据位进行编码，并因此利用上下文切换器中的解码器对编码的配置数据进行解码。

公开(公告)号：US20100228807A1

公开(公告)日：2010-09-09

申请号：US12380841

申请日：2009-03-03

申请人： Martin Langhammer ,  Yi-Wen Lin ,  Keone Streicher

发明人： Martin Langhammer ,  Yi-Wen Lin ,  Keone Streicher

IPC分类号： G06F7/00

CPC分类号： H03K5/1252 ,  G06F7/5324 ,  G06F2207/382 ,  H03K19/17732

摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect).

摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。

公开(公告)号：US07724028B1

公开(公告)日：2010-05-25

申请号：US12101375

申请日：2008-04-11

申请人： Ahmad R. Ansari ,  Alex S. Warshofsky

发明人： Ahmad R. Ansari ,  Alex S. Warshofsky

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K19/17732

摘要： An ASIC block embedded in a host IC has a first clock domain with a first frequency of operation that is at least equal to a second frequency of operation of a second clock domain in the host IC but external to the ASIC block. FPGA logic in the second clock domain interfaces with the ASIC block; and a PLL located in the host integrated circuit but external to the ASIC block is coupled to receive a reference clock signal and configured to generate clock signals. Two of the clock signals are respectively sent to the FPGA logic and the ASIC block to make one appear to be produced earlier in time than the other with respect to the ASIC block to compensate for a clock insertion delay and for a clock-to-output time associated with the FPGA logic that at least approximates zero.

摘要翻译： 嵌入在主机IC中的ASIC块具有第一时钟域，其具有至少等于主机IC中的第二时钟域的第二频率的操作的第一操作频率，但是在ASIC块的外部。 第二个时钟域的FPGA逻辑与ASIC块接口; 并且位于主机集成电路中但在ASIC块外部的PLL被耦合以接收参考时钟信号并被配置为产生时钟信号。 时钟信号中的两个分别被发送到FPGA逻辑和ASIC块，以使它们相对于ASIC块在时间上比另一个稍早地产生，以补偿时钟插入延迟和时钟到输出 与FPGA逻辑相关的时间至少近似为零。

公开(公告)号：US20100097099A1

公开(公告)日：2010-04-22

申请号：US12645236

申请日：2009-12-22

申请人： Deboleena Minz ,  Kailash Digari

发明人： Deboleena Minz ,  Kailash Digari

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17732

摘要： A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.

摘要翻译： 一种FPGA，包括用于提供选择性数据路由的直接互连结构，而不强调通用路由资源并且实现FPGA内的高速数据交换。 至少两个IP核通过所述直接互连结构相互连接，以便能够在所述IP核的端口之间同时进行数据交互，并且用于在所述IP核之间提供可配置的总线宽度路由，以及连接到所述IP核的多个逻辑块 通过所述直接互连结构来实现在所述IP核和所述多个逻辑块之间的同时数据路由。

公开(公告)号：US07696781B1

公开(公告)日：2010-04-13

申请号：US12291923

申请日：2008-11-14

申请人： Ali H. Burney ,  Daniel R. Mansur

发明人： Ali H. Burney ,  Daniel R. Mansur

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/17732

摘要： Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.

摘要翻译： 提供电路和方法来控制和配置PLD。 本发明的实施例包括嵌入在PLD中的硬IP电路。 电路可以包括千兆MAC，硬处理器和DMA引擎。 本发明允许多种操作，包括实时控制和远程编程，而不使用专用的外部电路。

公开(公告)号：US20100007379A1

公开(公告)日：2010-01-14

申请号：US12563634

申请日：2009-09-21

申请人： Martin Langhammer ,  Nitin Prasad

发明人： Martin Langhammer ,  Nitin Prasad

IPC分类号： H03K19/177 ,  G06F7/38

CPC分类号： G06F7/5095 ,  G06F5/015 ,  G06F7/53 ,  G06F7/575 ,  G06F7/724 ,  G06F15/7867 ,  G06F2207/3828 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/17736

摘要： A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.

摘要翻译： 可编程逻辑集成电路器件除了可编程逻辑的通常多个区域和通常的可编程逻辑器件之外，还具有至少一个功能特定电路块（例如，并行乘法器，并行桶形移位器，并行算术逻辑单元等） 互联电路资源。 为了减少使用功能特定块（“FSB”）对设备的通用互连资源的影响，FSB的输入和/或输出可以相对直接地耦合到逻辑区域的子集。 除了节省通用互连之外，FSB可以使用FSB连接的逻辑区域的资源，以减少必须专用于FSB的电路的数量。 如果FSB是乘法器，则附加特征包括促进连续乘法器输出的累积（如果需要，使用加法或减法和符号扩展）和/或算术组合多个乘法器的输出。

公开(公告)号：US07579895B2

公开(公告)日：2009-08-25

申请号：US11932807

申请日：2007-10-31

申请人： Shin-Nan Sun ,  Limin Zhu ,  Theodore Speers ,  Gregory Bakker

发明人： Shin-Nan Sun ,  Limin Zhu ,  Theodore Speers ,  Gregory Bakker

IPC分类号： H03K17/62

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

摘要翻译： 一种可编程片上系统集成电路器件，包括晶体振荡器电路，RC振荡器电路和外部振荡器输入中的至少一个。 时钟调理电路选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。 实时时钟可选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。 可编程逻辑块耦合到时钟调节电路和实时时钟。

公开(公告)号：US07573292B1

公开(公告)日：2009-08-11

申请号：US12032559

申请日：2008-02-15

申请人： Vi Chi Chan

发明人： Vi Chi Chan

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/17732

摘要： A system for providing a pre-programmed integrated circuit including programmable logic, and method for providing same. The system includes: nonvolatile memory capable of having first data stored therein and an integrated circuit coupled with the nonvolatile memory. The first data is associated with a predetermined design, and the integrated circuit includes programmable logic having a user region and a reserved region. The integrated circuit is configured to obtain the first data from the nonvolatile memory for instantiation of the predetermined design in the reserved region.

摘要翻译： 一种用于提供包括可编程逻辑的预编程集成电路的系统，以及用于提供其的方法。 该系统包括：能够存储第一数据的非易失性存储器和与非易失性存储器耦合的集成电路。 第一数据与预定的设计相关联，并且集成电路包括具有用户区域和保留区域的可编程逻辑。 集成电路被配置为从非易失性存储器获得用于在保留区域中预定设计的实例化的第一数据。

公开(公告)号：US07560954B2

公开(公告)日：2009-07-14

申请号：US12178874

申请日：2008-07-24

申请人： Rabindranath Balasubramanian ,  Limin Zhu ,  Gregory Bakker

发明人： Rabindranath Balasubramanian ,  Limin Zhu ,  Gregory Bakker

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log.

摘要翻译： 可编程片上系统集成电路器件包括可编程逻辑块，至少一个用户非易失性存储器块，以及在单个半导体集成电路芯片或倒装芯片上的温度感测和控制模拟和数字电路 面对或其他多模配置。 具有温度测量和控制电路的可编程片上系统芯片集成电路执行温度测量和控制功能，可用于创建片上温度记录。