公开(公告)号：US07619984B2

公开(公告)日：2009-11-17

申请号：US11215894

申请日：2005-08-30

Applicant: Richard D. Carmichael

Inventor： Richard D. Carmichael

IPC: H04L12/26 ,  H04J3/00 ,  H04J3/07 ,  G06F11/00 ,  H03M13/00

CPC classification number: H04L1/1829 ,  H04L1/08 ,  H04L1/201

Abstract: A method for error handling of corrupted repeating primitives during frame reception is disclosed. The method comprises identifying a portion of a received frame including a repeating primitive sequence, determining whether data in the repeating primitive sequence has one or more errors, and indicating a successful reception of the received frame with the one or more errors in the repeating primitive sequence if the number of errors is less than a determined threshold. Other embodiments are also disclosed.

Abstract translation: 公开了一种在帧接收期间错误处理损坏的重复原语的方法。 该方法包括识别包括重复原语序列的接收帧的一部分，确定重复原语序列中的数据是否具有一个或多个错误，并且指示接收的帧的成功接收与重复的基本序列中的一个或多个错误 如果错误的数量小于确定的阈值。 还公开了其他实施例。

公开(公告)号：US07593427B1

公开(公告)日：2009-09-22

申请号：US09962047

申请日：2001-09-21

Applicant: Harris Wongsonegoro ,  Edgar Abadines ,  Marc A. Bennett

Inventor： Harris Wongsonegoro ,  Edgar Abadines ,  Marc A. Bennett

IPC: H04J3/07 ,  H04L12/28 ,  G06F15/16

CPC classification number: H04L43/18 ,  H04L41/0806 ,  H04L41/0879 ,  H04L41/0886 ,  H04L43/045

Abstract: Methods and apparatus for automatically detecting the frame format of a data signal and automatically provisioning a port based on the detected frame format are disclosed. According to one aspect of the present invention, a framing format detection mechanism that is suitable for use in a network within which a data signal is arranged to be transmitted includes a first device and a second device. The first device is arranged to be a part of a line card and in communication with a signal receiving port on the line card. The first device is also arranged to automatically determine a frame format associated with the data signal. The second device is arranged to display the frame format associated with the data signal substantially in real-time. In one embodiment, the first device is further arranged to automatically provision the port.

Abstract translation: 公开了一种用于自动检测数据信号的帧格式并基于检测到的帧格式自动提供端口的方法和装置。 根据本发明的一个方面，一种适用于其中要发送数据信号的网络中的帧格式检测机构包括第一装置和第二装置。 第一装置被布置成是线卡的一部分并且与线卡上的信号接收端口通信。 第一设备还被布置成自动地确定与数据信号相关联的帧格式。 第二装置被布置为基本上实时地显示与数据信号相关联的帧格式。 在一个实施例中，第一设备还被布置成自动提供端口。

公开(公告)号：US07564875B2

公开(公告)日：2009-07-21

申请号：US10706356

申请日：2003-11-11

Applicant: Niklas Linkewitsch ,  Michael Kauschke

Inventor： Niklas Linkewitsch ,  Michael Kauschke

IPC: H04J3/07

CPC classification number: H04J3/167 ,  H04J3/0685 ,  H04J3/07 ,  H04J3/1611 ,  H04L12/66

Abstract: Briefly, a system that maps SONET/SDH data to an OTN frame using justification commands. Briefly, a system that de-maps an OTN frame into SONET/SDH data using justification commands.

Abstract translation: 简而言之，使用调整命令将SONET / SDH数据映射到OTN帧的系统。 简而言之，使用调整命令将OTN帧解映射成SONET / SDH数据的系统。

公开(公告)号：US07535932B2

公开(公告)日：2009-05-19

申请号：US11019350

申请日：2004-12-23

Applicant: Minami Ishii ,  Sung Uk Moon ,  Takehiro Nakamura ,  Anil Umesh

Inventor： Minami Ishii ,  Sung Uk Moon ,  Takehiro Nakamura ,  Anil Umesh

IPC: H04W4/00 ,  H04J3/06 ,  H04J3/07 ,  H04W72/00

CPC classification number: H04W48/12 ,  H04W56/00 ,  H04W88/12 ,  H04W92/12

Abstract: The present invention relates to a radio communications system which transmits same downlink information to a plurality of cells by using downlink common channels. The radio communications system includes a radio network controller and a base station. The radio communications system is configured to measure delays between the time when the radio network controller transmits the downlink information and the time when the base station transmits the downlink information to each of the plurality of cells; and to control timing for transmitting the downlink information to each of the plurality of cells by the base station in accordance with measured delays.

Abstract translation: 本发明涉及通过使用下行链路公共信道向多个小区发送相同的下行链路信息的无线通信系统。 无线电通信系统包括无线电网络控制器和基站。 无线电通信系统被配置为测量无线电网络控制器发送下行链路信息的时间与基站向多个小区中的每一个发送下行链路信息的时间之间的延迟; 并且根据测量的延迟来控制由基站将下行链路信息发送到多个小区中的每一个的定时。

公开(公告)号：US07532645B1

公开(公告)日：2009-05-12

申请号：US11035613

申请日：2005-01-14

Applicant: Khaldoun Bataineh ,  Stephen D. Anderson ,  Michael Maas ,  David E. Tetzlaff

Inventor： Khaldoun Bataineh ,  Stephen D. Anderson ,  Michael Maas ,  David E. Tetzlaff

IPC: H04J3/07

CPC classification number: H04L7/0338

Abstract: A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

Abstract translation: 一种接收机，包括：过采样模块，其基于所述接收时钟将串行数据流转换为多个过采样数据流; 转移位置模块，其确定过采样数据流和接收时钟的转换位置; 指针调整模块，其基于所述转换位置和所述接收时钟来确定指针变量; 数据选择模块，其基于指针变量确定过采样数据流的等效数据值; 分级寄存器模块，用于从过采样数据流的等效数据值产生偏移数据字和额外的数据字; 以及输出寄存器模块，其从偏移数据字和额外数据字中的至少一个产生并行数据输出。

公开(公告)号：US20080253405A1

公开(公告)日：2008-10-16

申请号：US11735085

申请日：2007-04-13

Applicant: Patrick Ng ,  Paul Chow

Inventor： Patrick Ng ,  Paul Chow

IPC: H04J3/07

CPC classification number: H04N21/2389 ,  H04N21/23412 ,  H04N21/4382 ,  H04N21/4385 ,  H04N21/4425

Abstract: A method and system for providing error resiliency in processing a multimedia bitstream. The bitstream includes a start code pattern and the method and system detect the start code pattern and track its location to prevent the bitstream processor from overrunning the start code pattern of a subsequent block of multimedia data and corrupting the subsequent block of data. A shift length limiter receives a location of the start code pattern and the location of a current bit pointer. The shift length limiter calculates the number of bits between the start code pattern location and the current bit pointer location. When the shift length limiter receives a bit shift request, the shift length limiter prevents shifting if the number of bits in the bit shift request exceeds the calculated number of bits between the start code pattern location and the current bit pointer location.

Abstract translation: 一种用于在处理多媒体比特流中提供错误弹性的方法和系统。 比特流包括起始码模式，并且该方法和系统检测起始码模式并跟踪其位置，以防止比特流处理器超越后续多媒体数据块的起始码模式并破坏随后的数据块。 移位长度限制器接收起始码模式的位置和当前位指针的位置。 移位长度限制器计算起始码模式位置和当前位指针位置之间的位数。 当移位限制器接收到比特移位请求时，如果比特移位请求中的比特数超过了开始码模式位置和当前比特指针位置之间的计算比特数，则移位长度限制器防止移位。

公开(公告)号：US07379480B2

公开(公告)日：2008-05-27

申请号：US10347658

申请日：2003-01-16

Applicant: Sivaram Balasubramanian ,  Kendal R. Harris

Inventor： Sivaram Balasubramanian ,  Kendal R. Harris

IPC: H04J3/07 ,  H04J3/06

CPC classification number: H04J3/0667 ,  H04J3/0697

Abstract: A method of precisely synchronizing clocks held in separate nodes on a communication network is provided that adjusts clock frequency based on a measure of relative clock rates and absolute clock offsets. In one embodiment, clock convergence is obtained with one synchronization session.

Abstract translation: 提供了精确地同步在通信网络上的分离节点中的时钟的方法，其基于相对时钟速率和绝对时钟偏移的测量来调整时钟频率。 在一个实施例中，通过一个同步会话获得时钟收敛。

公开(公告)号：US20080075125A1

公开(公告)日：2008-03-27

申请号：US11525656

申请日：2006-09-22

Applicant: Ravi Subrahmanyan ,  Venkat Sreenivas

Inventor： Ravi Subrahmanyan ,  Venkat Sreenivas

IPC: H04J3/07

CPC classification number: H04J3/1611 ,  H04J3/076

Abstract: A system and method are provided for a sampled accumulation method that maps information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries, and sequentially stores buffer-fill information for each tributary in a first memory, at a rate of up to one tributary per system clock (Fsys) cycle. A stored accumulation of buffer-fill information for each tributary is updated at a sample rate frequency (Fsample), where Fsample≦Fsys. The stored accumulation of buffer-fill information is used to calculate stuff bit opportunities for each tributary. As a result, the rate of data being mapped into outgoing tributaries is regulated, and the outgoing mapped tributaries are combined in a SPE.

Abstract translation: 提供了一种用于将信息映射到同步有效载荷包络（SPE）的采样累积方法的系统和方法。 该方法缓冲来自多个支路的数据，并且以每个系统时钟（Fsys）周期最多一个支路的速率，顺序地将每个支路的缓冲区填充信息存储在第一存储器中。 每个支流的缓冲区填充信息的存储积累以采样率频率（Fsample）更新，其中Fsample = Fsys。 缓冲区填充信息的存储积累用于计算每个支流的填充位机会。 因此，映射到出站支路的数据速率受到限制，出站映射支路在SPE中组合。

公开(公告)号：US07346079B1

公开(公告)日：2008-03-18

申请号：US10829037

申请日：2004-04-20

Applicant: Jerome M. Meyer

Inventor： Jerome M. Meyer

IPC: H04J3/00 ,  H04J3/16 ,  H04J3/22 ,  H04J3/24 ,  H04J3/07

CPC classification number: H04J3/0605 ,  H04J3/0623 ,  H04J3/1611

Abstract: Methods and structures of performing multi-level comma detection and alignment on an unaligned data stream. Each string of N consecutive bits in the unaligned data stream is monitored for a predetermined byte value. When the predetermined byte value is located, the unaligned data stream is aligned with the predetermined byte value, producing a partially aligned data stream. A string of bytes from the partially aligned data stream is then compared with a predetermined sequence of byte values. When the predetermined sequence is located, the partially aligned data stream is aligned based on the location of the predetermined sequence within the partially aligned data stream. The invention also encompasses multi-level comma detection and alignment circuits that can perform, for example, the previously described inventive methods.

Abstract translation: 在未对齐的数据流上执行多级逗号检测和对齐的方法和结构。 监视未对齐数据流中的每个N个连续比特串，以获得预定的字节值。 当预定的字节值被定位时，未对齐的数据流与预定的字节值对准，产生部分对齐的数据流。 然后将来自部分对准的数据流的一串字节与预定的字节值序列进行比较。 当预定序列被定位时，部分对准的数据流基于部分对准的数据流内的预定序列的位置来对齐。 本发明还包括可以执行例如先前描述的本发明方法的多级逗号检测和对准电路。

公开(公告)号：US07095816B2

公开(公告)日：2006-08-22

申请号：US10092089

申请日：2002-03-05

Applicant: Keiji Kishine ,  Haruhiko Ichino

Inventor： Keiji Kishine ,  Haruhiko Ichino

IPC: H04L7/00 ,  H04J3/07 ,  H03L7/00

CPC classification number: H04L7/0337 ,  H03L7/08 ,  H04J3/047

Abstract: A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of an input data signal; a delay circuit; a demultiplexer for demultiplexing the input data signal; a multiplexer for multiplexing the demultiplexed signals; a phase comparator for comparing phases of an output signal of the delay circuit and an output signal of the multiplexer; a lowpass filter; wherein the clock/data recovery circuit outputs the clock signal generated by the voltage control oscillator as a recovery divided clock signal, and outputs the demultiplexed signals output as recovery parallel data signals.