公开(公告)号：US11751402B2

公开(公告)日：2023-09-05

申请号：US16636199

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： Abhishek A. Sharma

IPC分类号： H10B53/30 ,  G11C7/18 ,  G11C8/14 ,  G11C11/22 ,  H01L29/423

CPC分类号： H10B53/30 ,  G11C7/18 ,  G11C8/14 ,  G11C11/221 ,  G11C11/223 ,  H01L29/42384

摘要： An integrated circuit includes a backend thin-film transistor (TFT) a ferroelectric capacitor electrically connected to the backend TFT. The backend TFT has a gate electrode, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, and a gate dielectric between the gate electrode and semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source and drain regions, a second terminal, and a ferroelectric dielectric between the first and second terminals. In an embodiment, a memory cell includes this integrated circuit, the gate electrode being electrically connected to a wordline, the source region being electrically coupled to a bitline, and the drain region being the one of the source and drain regions. In an embodiment, an embedded memory includes wordlines, bitlines, and a plurality of such memory cells at crossing regions of the wordlines and bitlines.

公开(公告)号：US20230230624A1

公开(公告)日：2023-07-20

申请号：US17415657

申请日：2021-01-26

申请人： MICRON TECHNOLOGY, INC.

发明人： Jiangang Wu ,  Lei Zhou ,  Jung Sheng Hoei ,  Kishore Kumar Muchherla ,  Qisong Lin

IPC分类号： G11C7/10 ,  G11C8/08 ,  G11C8/14

CPC分类号： G11C7/1096 ,  G11C8/08 ,  G11C8/14

摘要： A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.

公开(公告)号：US11696440B2

公开(公告)日：2023-07-04

申请号：US17728290

申请日：2022-04-25

申请人： KEY FOUNDRY CO., LTD.

发明人： Min Kuck Cho ,  Seung Hoon Lee

IPC分类号： H10B41/20 ,  G11C8/14 ,  G11C7/18 ,  H10B41/10

CPC分类号： H10B41/20 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10

摘要： A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer.

公开(公告)号：US20230180452A1

公开(公告)日：2023-06-08

申请号：US17956102

申请日：2022-09-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kiseok LEE ,  Taegyu KANG ,  Keunnam KIM ,  Sung-Min PARK ,  Taehyun AN ,  Sanghyun LEE ,  Eunsuk JANG ,  Moonyoung JEONG ,  Euichul JEONG ,  Hyungeun CHOI

IPC分类号： H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

CPC分类号： H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.

公开(公告)号：US20230143797A1

公开(公告)日：2023-05-11

申请号：US18153420

申请日：2023-01-12

申请人： Changxin Memory Technologies, Inc.

发明人： Sungsoo Chi ,  Fengqin Zhang ,  Shuyan Jin

IPC分类号： G11C8/08 ,  G11C8/14

CPC分类号： G11C8/08 ,  G11C8/14

摘要： Embodiments of the present disclosure provide a word line driver, a word line driver array, and a semiconductor structure, relating to the technical field of semiconductors. The word line driver includes: a zeroth P-channel metal oxide semiconductor (PMOS) transistor, a zeroth N-channel metal oxide semiconductor (NMOS) transistor, and a first NMOS transistor, the zeroth PMOS transistor being provided with a gate connected to a gate of the first NMOS transistor and configured to receive a first control signal, a source configured to receive a second control signal, and a drain connected to a drain of the first NMOS transistor, the zeroth NMOS transistor being provided with a gate configured to receive a second control complementary signal, and a drain of the zeroth NMOS transistor and the drain of the first NMOS transistor being configured to be connected to a word line.

公开(公告)号：US20230139346A1

公开(公告)日：2023-05-04

申请号：US17549685

申请日：2021-12-13

申请人： Intel Corporation

发明人： Liu LIU ,  Junchao DING ,  Yingming LIU ,  Jong Sun SEL ,  Yixin MA ,  Jinwoo LEE ,  Xi LIN

IPC分类号： G11C16/04 ,  G11C8/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

摘要： An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.

公开(公告)号：US11641734B2

公开(公告)日：2023-05-02

申请号：US17659493

申请日：2022-04-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Szu-Yao Chang

IPC分类号： G11C8/14 ,  G11C11/402 ,  H01L49/02

摘要： A method of forming a semiconductor structure includes forming a capacitor on a substrate. A recess is formed in the capacitor. A drain region is formed in the recess. A word line is formed on the drain region. A gate structure is formed on the drain region, and the gate structure is electrically connected to the word line. A first bit line is formed on the gate structure, such that the first bit line servers as a source region.

公开(公告)号：US20230066312A1

公开(公告)日：2023-03-02

申请号：US17553772

申请日：2021-12-16

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Hongbin Zhu ,  Wei Liu ,  Yanhong Wang

IPC分类号： H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  G11C7/18 ,  G11C8/14

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with a plurality of sides of the semiconductor body. One end of the semiconductor body coupled to the storage unit is flush with the gate structure. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

公开(公告)号：US20230030836A1

公开(公告)日：2023-02-02

申请号：US17813147

申请日：2022-07-18

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Guifen YANG ,  SUNGSOO CHI

IPC分类号： G11C8/08 ,  G11C8/14 ,  H01L27/02

摘要： A word line driver circuit may at least include multiple word line drivers, each of which including a PMOS transistor and at least one NMOS transistor. The multiple word line drivers include multiple PMOS transistors and multiple NMOS transistors. The multiple PMOS transistors are arranged side by side, and in an arrangement direction of the multiple PMOS transistors, a part of the multiple NMOS transistors are located on a side of the multiple PMOS transistors, and another part of the NMOS transistors are located on another side of the multiple PMOS transistors.

公开(公告)号：US11563005B2

公开(公告)日：2023-01-24

申请号：US16930398

申请日：2020-07-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Minsu Lee ,  Kiseok Lee ,  Minwoo Song ,  Hyun-Sil Oh ,  Min Hee Cho

IPC分类号： H01L27/108 ,  G11C8/14 ,  G11C7/18

摘要： A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern.