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公开(公告)号：US20240312494A1
公开(公告)日：2024-09-19
申请号：US18675997
申请日：2024-05-28
发明人： Shuai Xu , Michele Piccardi , Arvind Muralidharan , June Lee , Qisong Lin , Scott A. Stoller , Jun Shen
IPC分类号： G11C5/14
摘要： In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.
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2.发明公开公开(公告)号：US20240103749A1
公开(公告)日：2024-03-28
申请号：US18526103
申请日：2023-12-01
发明人： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
CPC分类号： G06F3/0647 , G06F3/0619 , G06F3/0673 , G06F11/1068 , G06F11/1402 , G11C29/52
摘要： At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
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公开(公告)号：US20230297511A1
公开(公告)日：2023-09-21
申请号：US18124447
申请日：2023-03-21
发明人： Jiangang Wu , Qisong Lin , Jung Sheng Hoei , Yunqiu Wan , Ashutosh Malshe , Peng-Cheng Chen
IPC分类号： G06F12/0891 , G06F12/0811 , G06F12/02 , G06F12/0882 , G06F11/14
CPC分类号： G06F12/0891 , G06F12/0811 , G06F12/0246 , G06F12/0882 , G06F11/14 , G11C16/06
摘要： Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.
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公开(公告)号：US11698864B2
公开(公告)日：2023-07-11
申请号：US17824676
申请日：2022-05-25
IPC分类号： G06F12/00 , G06F12/0882 , G06F12/02 , G11C11/408 , G06F9/30 , G06F9/4401
CPC分类号： G06F12/0882 , G06F9/30047 , G06F9/30098 , G06F9/4418 , G06F12/0246 , G11C11/4085
摘要： A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.
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公开(公告)号：US11455109B2
公开(公告)日：2022-09-27
申请号：US17160144
申请日：2021-01-27
IPC分类号： G06F3/06
摘要： A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.
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公开(公告)号：US20220129204A1
公开(公告)日：2022-04-28
申请号：US17516009
申请日：2021-11-01
发明人： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
IPC分类号： G06F3/06
摘要： An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
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公开(公告)号：US20210311649A1
公开(公告)日：2021-10-07
申请号：US17350866
申请日：2021-06-17
发明人： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
摘要： At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
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公开(公告)号：US20210193199A1
公开(公告)日：2021-06-24
申请号：US16946305
申请日：2020-06-16
IPC分类号： G11C7/10 , G06F9/30 , G06F11/27 , G06F12/0882
摘要： A programmable memory device includes a read only memory (ROM) block to store instructions associated with functionality of the programmable memory device. The device includes a memory array having a set of reserved pages to store updates to be performed on the ROM block. The device includes a controller coupled to the ROM block and the memory array. The controller is to execute the instructions to: execute a set features command; program, in execution of the set features command, a set of sub-feature parameters to a specified feature address of the set of reserved pages, wherein the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and program a REM-profiled page of the set of reserved pages with REM data received from a host system.
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公开(公告)号：US20200026462A1
公开(公告)日：2020-01-23
申请号：US16041649
申请日：2018-07-20
发明人： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
IPC分类号： G06F3/06
摘要： An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
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公开(公告)号：US20190243704A1
公开(公告)日：2019-08-08
申请号：US16045641
申请日：2018-07-25
发明人： Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Peter Feeley , Sampath K. Ratnam , Sivagnanam Parthasarathy , Qisong Lin , Shane Nowell , Mustafa N. Kaynak
CPC分类号： G06F11/0793 , G06F3/0619 , G06F3/0634 , G06F3/0679 , G06F11/073 , G06F11/076 , G06F11/079 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26
摘要： A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
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