中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

1078 records (took 0.039 seconds)

    OPTOELECTRONIC DEVICE
    294.
    发明申请
    OPTOELECTRONIC DEVICE 有权

    公开(公告)号：US20210135069A1

    公开(公告)日：2021-05-06

    申请号：US17071603

    申请日：2020-10-15

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Romain COFFY ,  Remi BRECHIGNAC ,  Jean-Michel RIVIERE

    IPC: H01L33/54 ,  H01L33/00

    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill.

    DEPTH MAP SENSOR WITH BIN ROTATION
    295.
    发明申请
    DEPTH MAP SENSOR WITH BIN ROTATION 有权

    公开(公告)号：US20210133992A1

    公开(公告)日：2021-05-06

    申请号：US17074238

    申请日：2020-10-19

    Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMicroelectronics (Grenoble 2) SAS

    Inventor： Ivelina Hristova ,  Pascal Mellot ,  Neale Dutton

    IPC: G06T7/50 ,  G06F1/10 ,  G06T15/08 ,  G06T15/00

    Abstract: A depth map sensor includes a first array of first pixels, each first pixel having a first photodetector associated with a pixel circuit that comprises a plurality of first bins for accumulating events. A clock source is configured to generate a plurality of phase-shifted clock signals. A first circuit has a plurality of first output lines coupled to the first array of first pixels. The first circuit is configured to receive the plurality of phase-shifted clock signals. The first circuit includes a first block and a second block. The first block is configured to propagate the plurality of phase-shifted clock signals to the second block during a first period determined by a first enable signal and the second block configured to select to which of the plurality of first output lines each of the plurality of phase-shifted clock signals is applied.

    Direct memory access
    296.
    发明授权
    Direct memory access 有权

    公开(公告)号：US10997087B2

    公开(公告)日：2021-05-04

    申请号：US16511362

    申请日：2019-07-15

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： François Cloute

    IPC: G06F12/1081 ,  G06F3/06

    Abstract: A system includes a direct memory access controller and a memory coupled to the direct memory access controller. The memory stores a linked list of records. Each record contains a first field determining the number of fields of a next record. For example, each record can be representative of parameters of execution of a data transfer by the direct memory access controller.

Patent Agency Ranking