中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

1956 records (took 0.051 seconds)

    IMAGE SENSOR DEVICE WITH MACROPIXEL PROCESSING AND RELATED DEVICES AND METHODS
    292.
    发明申请
    IMAGE SENSOR DEVICE WITH MACROPIXEL PROCESSING AND RELATED DEVICES AND METHODS 审中-公开

    公开(公告)号：US20180241975A1

    公开(公告)日：2018-08-23

    申请号：US15958244

    申请日：2018-04-20

    Applicant: STMicroelectronics International N.V.

    Inventor： Mahesh Chandra ,  Brejesh Lall

    IPC: H04N9/04 ,  H04N5/347

    CPC classification number: H04N9/045 ,  H04N5/347

    Abstract: An image sensor device may include an array of image sensing pixels with adjacent image sensing pixels being arranged in macropixel, and a processor coupled to the array of image sensing pixels. The processor may be configured to receive pixel signals from the array of image sensing pixels, and arrange the received pixel signals into macropixel signal sets for respective macropixels. The processor may be configured to perform, in parallel, an image enhancement operation on the received pixel signals for each macropixel signal set to generate enhanced macropixel signals, and transmit the enhanced macropixel signals.

    Polyphase decimation FIR filters and methods
    293.
    发明授权
    Polyphase decimation FIR filters and methods 有权

    公开(公告)号：US10050607B2

    公开(公告)日：2018-08-14

    申请号：US14573055

    申请日：2014-12-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Neha Bhargava ,  Ankur Bal

    IPC: H03H17/06 ,  H03H17/02

    Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

    Stuck-at fault detection on the clock tree buffers of a clock source
    294.
    发明授权
    Stuck-at fault detection on the clock tree buffers of a clock source 有权

    公开(公告)号：US10048315B2

    公开(公告)日：2018-08-14

    申请号：US15203362

    申请日：2016-07-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Venkata Narayanan Srinivasan

    IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185

    Abstract: A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).

    PARALLEL PIPELINE LOGIC CIRCUIT FOR GENERATING CRC VALUES UTILIZING LOOKUP TABLE
    297.
    发明申请
    PARALLEL PIPELINE LOGIC CIRCUIT FOR GENERATING CRC VALUES UTILIZING LOOKUP TABLE 审中-公开

    公开(公告)号：US20180175883A1

    公开(公告)日：2018-06-21

    申请号：US15381516

    申请日：2016-12-16

    Applicant: STMicroelectronics International N.V.

    Inventor： Tejinder Kumar ,  Rakesh Malik

    IPC: H03M13/09 ,  G06F11/10 ,  H03M13/00

    CPC classification number: H03M13/091 ,  G06F11/1004 ,  H03M13/6505

    Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.

Patent Agency Ranking