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291.发明授权Hysteresis comparator circuit having differential input transistors with switched bulk bias voltages 有权迟滞比较器电路具有开关体积偏置电压的差分输入晶体管公开(公告)号：US09432015B2
公开(公告)日：2016-08-30
申请号：US14153119
申请日：2014-01-13
Applicant: STMicroelectronics International N.V.
Inventor： Pijush Kanti Panja , Rajesh Yadav
IPC: H03K5/22 , H03K17/687 , H03F3/45 , H03K5/24 , H03K3/3565
CPC classification number: H03K17/687 , H03F3/45183 , H03F3/45753 , H03F2200/447 , H03F2203/45341 , H03K3/3565 , H03K5/2481
Abstract: A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages.
Abstract translation: 将在第一晶体管处接收的第一信号与在第二晶体管处接收的第二信号进行比较，考虑滞后值以产生比较输出。 第一和第二晶体管中的至少一个具有浮动体积。 开关电路根据比较输出选择性地将第一和第二体偏置电压施加到第一或第二晶体管的浮动体。 设置滞后值的第三和第四输入信号在第三和第四晶体管处被接收，并被比较以产生差分输出。 第三和第四晶体管中的至少一个具有浮动体积。 差分放大器确定用于施加到第三和第四晶体管中的至少一个的浮动体的差分输出之间的差异，并进一步用作第一和第二体偏置电压之一。
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公开(公告)号：US09432008B2
公开(公告)日：2016-08-30
申请号：US14337896
申请日：2014-07-22
Inventor： Stéphane Le Tual , Pratap Narayan Singh
CPC classification number: H03K5/134 , H03K5/13 , H03K2005/00032 , H03K2005/00208 , H03K2005/00215 , H03K2217/0018
Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.
Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。
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293.发明授权Memory encryption method compatible with a memory interleaved system and corresponding system 有权内存加密方法与内存交错系统和相应系统兼容公开(公告)号：US09419952B2
公开(公告)日：2016-08-16
申请号：US14645688
申请日：2015-03-12
Inventor： Ignazio Antonino Urzi , Asif Rashid Zargar
CPC classification number: H04L63/0464 , G06F12/1408 , G06F21/71 , G06F21/79 , H04L9/0618 , H04L63/061
Abstract: A method for managing an operation of an encrypted global interleaved memory space physically implemented according to an interleaving addressing scheme in encrypted memory banks of a plurality of memories respectively belonging to a plurality of channels. The method includes providing each channel with a local address pointer configured to be incrementally moved along the global memory space each time the global memory space is addressed at the current address pointed by the pointer, and in an absence of movement of the local pointer of a channel during a time period, addressing the global memory space from the channel through the address interleaving with a specific transaction at the current address, and upon reception at the channel of the specific transaction having been initiated by the channel, re-encrypting data located at the current address with a new encryption key and incrementing the local address pointer to its next position.
Abstract translation: 一种用于管理分别属于多个信道的多个存储器的加密存储体中根据交错寻址方案物理地实现的加密的全局交错存储器空间的操作的方法。 该方法包括向每个信道提供本地地址指针，该本地地址指针被配置成每当在指针指向的当前地址处寻址全局存储空间时，沿着全局存储器空间递增地移动，并且在局部指针的移动 在通过与当前地址的特定事务进行地址交织的情况下，从信道寻址全局存储器空间，以及在由信道发起的特定事务的信道的接收时，重新加密位于 当前地址使用新的加密密钥，并将本地地址指针递增到其下一个位置。
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公开(公告)号：US09419634B1
公开(公告)日：2016-08-16
申请号：US14752226
申请日：2015-06-26
Inventor： Sebastien Dedieu , Abhirup Lahiri
CPC classification number: H03K3/0315 , H03K3/013 , H03L1/02 , H03L7/00 , H03L7/0805 , H03L7/24
Abstract: A multiple phase oscillator includes a master oscillator that injection locks a first ring oscillator. The free-running frequency of the first ring oscillator is adjustable through a control signal. A second ring oscillator has a same structure as the first ring oscillator and is connected to operate in a free-running mode. The free-running frequency of the second ring oscillator is adjustable through the control signal. A control loop senses the output of the second ring oscillator and adjusts the control signal so that the free-running frequency of the second ring oscillator matches a desired value.
Abstract translation: 多相振荡器包括一个主振荡器，该主振荡器注入锁定第一个环形振荡器。 第一个环形振荡器的自由运行频率可通过控制信号进行调节。 第二环形振荡器具有与第一环形振荡器相同的结构，并连接以工作在自由运行模式。 第二个环形振荡器的自由运行频率可以通过控制信号进行调节。 控制回路感测第二环形振荡器的输出并调整控制信号，使得第二环形振荡器的自由运行频率与期望值相匹配。
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295.发明授权High frequency low-gain noise ring-type VCO oscillator leading to a low-noise/area PLL 有权高频低增益噪声环型VCO振荡器导致低噪声/区域PLL公开(公告)号：US09401699B2
公开(公告)日：2016-07-26
申请号：US14090759
申请日：2013-11-26
Applicant: STMicroelectronics International N.V.
Inventor： Amit Katyal
CPC classification number: H03K3/0315 , G05F3/262 , H03L7/0995
Abstract: A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.
Abstract translation: 锁相环包括压控振荡器和向压控振荡器提供驱动电流的电流镜电路。 电流镜电路包括偏置电流发生器和电流镜晶体管之间的滤波器。 该滤波器包括以小占空比同时驱动的第一和第二开关。
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Patent Agency Ranking
公开(公告)号：US09395730B2
公开(公告)日：2016-07-19
申请号：US13929549
申请日：2013-06-27
Applicant: STMicroelectronics International N.V.
Inventor： Saurabh Kumar Singh , Nitin Bansal , Kallol Chatterjee
Abstract: A method and apparatus are provided. The apparatus includes a plurality of devices forming a positive feedback loop for driving a regulated output voltage towards a reference voltage. Device ratios of at least two of the plurality of devices are set such that the positive feedback loop is stable.
Abstract translation: 提供了一种方法和装置。 该装置包括多个装置，其形成用于将调节的输出电压朝向参考电压驱动的正反馈回路。 设置多个装置中的至少两个装置的装置比，使得正反馈环路是稳定的。
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297.发明授权Methodology to avoid gate stress for low voltage devices in FDSOI technology 有权在FDSOI技术中避免低压器件栅极应力的方法公开(公告)号：US09385708B2
公开(公告)日：2016-07-05
申请号：US14216701
申请日：2014-03-17
Applicant: STMicroelectronics International N.V.
Inventor： Ankit Agrawal
IPC: H01L27/12 , H01L29/786 , H03K3/00 , H03K17/687 , H03K17/10 , H01L29/10 , H01L29/423 , H01L27/092
CPC classification number: H03K17/102 , H01L27/092 , H01L27/1203 , H01L29/0653 , H01L29/1033 , H01L29/42364 , H01L29/7838 , H01L29/78648 , H03K17/6872
Abstract: An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.
Abstract translation: 逆变器在FDSOI集成电路管芯中实现。 反相器包括PMOS晶体管和NMOS晶体管。 PMOS和NMOS晶体管各自包括耦合到晶体管的相应源极端子的第一栅极。 PMOS和NMOS晶体管各自包括耦合到反相器的输入的背栅。
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公开(公告)号：US09331681B2
公开(公告)日：2016-05-03
申请号：US14072373
申请日：2013-11-05
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Archit Joshi
IPC: H03K3/84
CPC classification number: H03K3/84
Abstract: In accordance with an embodiment, a method of generating noise includes generating, using a hardware-based noise generator, a plurality of periodic waveforms having different frequencies, weighting, using the hardware-based noise generator, amplitudes of the plurality of periodic waveforms based on a predetermined spectral shape to form a plurality of weighted waveforms, and summing the plurality of plurality of weighted waveforms to form an output random noise signal.
Abstract translation: 根据实施例，一种产生噪声的方法包括：使用基于硬件的噪声发生器生成具有不同频率的多个周期性波形，使用基于硬件的噪声发生器对多个周期波形的幅度进行加权，基于 预定的光谱形状以形成多个加权波形，并且对多个加权波形进行求和以形成输出随机噪声信号。
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公开(公告)号：US20160105017A1
公开(公告)日：2016-04-14
申请号：US14509427
申请日：2014-10-08
Inventor： Ranajay Mallik , Luigi Abbatelli , Giuseppe Catalisano , Akshat Jain
CPC classification number: H02H7/205 , H02H1/0007 , H03K17/0828 , H03K17/166 , H03K17/168 , H05B6/062
Abstract: A drive transistor is connected to a resonant load in a low-side drive configuration. The voltage across the conduction terminals of the drive transistor is sensed and compared to an over-voltage threshold. An over-voltage signal is asserted in response to the comparison. The drive transistor is controlled by a PWM control signal in normal mode. In response to the assertion of the over-voltage signal, the drive transistor is forced to turn on (irrespective of the PWM control signal) to relieve the over-voltage condition. Operation of the circuit may be disabled or forced into soft start mode in response to the assertion of the over-voltage signal. Additionally, the pulse width of the PWM control signal may be reduced in response to the assertion of the over-voltage signal.
Abstract translation: 驱动晶体管以低侧驱动配置连接到谐振负载。 检测驱动晶体管的导通端子两端的电压并将其与过电压阈值进行比较。 响应于比较来断言过电压信号。 驱动晶体管由正常模式下的PWM控制信号控制。 响应于过电压信号的断言，驱动晶体管被强制导通（不管PWM控制信号如何）以减轻过电压状况。 响应于过电压信号的断言，电路的操作可能被禁用或强制进入软启动模式。 此外，可以响应于过电压信号的断言而减小PWM控制信号的脉冲宽度。
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公开(公告)号：US09306605B1
公开(公告)日：2016-04-05
申请号：US14596026
申请日：2015-01-13
Applicant: STMicroelectronics International N.V.
Inventor： Roland Van Der Tuijn , Yoann Bouvet
Abstract: An electronic device includes a radio configured to operate at an operating frequency, and a first universal asynchronous receiver/transmitter (UART) configured to operate as a master and at a baud rate. The electronic device also includes a second UART configured to communicate with the first UART, operating as a slave. The second UART has a controller configured to generate a frequency shift based upon the operating frequency of the radio being evenly divisible by the baud rate, and a baud clock generator. The baud clock generator is configured to generate an operating baud rate from a master clock signal, with the operating baud rate to be the baud rate shifted by the frequency shift. Transmitter circuitry is configured to operate based on the operating baud rate, and receiver circuitry is configured to operate based on the operating baud rate.
Abstract translation: 电子设备包括被配置为以工作频率工作的无线电设备和被配置为作为主设备以波特率操作的第一通用异步接收器/发射器（UART）。 电子设备还包括被配置为与作为从设备操作的第一UART进行通信的第二UART。 第二UART具有控制器，该控制器被配置为基于可被波特率均匀分割的无线电的工作频率和波特率时钟发生器产生频移。 波特率时钟发生器配置为从主时钟信号生成工作波特率，工作波特率为波特率移位频移。 发送器电路被配置为基于操作波特率进行操作，并且接收器电路被配置为基于操作波特率进行操作。
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