公开(公告)号：US11038092B2

公开(公告)日：2021-06-15

申请号：US16448544

申请日：2019-06-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Philipp Steinmann ,  Puneet H. Suvarna

IPC: H01L35/32 ,  H01L35/22 ,  H01L35/34 ,  H01L27/105

Abstract: Structures that include semiconductor fins and methods for forming a structure that includes semiconductor fins. A first fin comprised of n-type semiconductor material and a second fin comprised of p-type semiconductor material are formed. A conductive strap is formed that couples an end of the first fin with an end of the second fin.

公开(公告)号：US11037906B2

公开(公告)日：2021-06-15

申请号：US16447335

申请日：2019-06-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Luke G. England

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/78 ,  H01L21/56

Abstract: A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.

公开(公告)号：US20210141610A1

公开(公告)日：2021-05-13

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: G06F7/58 ,  H04L9/32 ,  H01L29/772 ,  H01L27/07 ,  H01L21/8234

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US11004953B2

公开(公告)日：2021-05-11

申请号：US16454016

申请日：2019-06-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Rinus Tek Po Lee ,  Hui Zang ,  Jiehui Shu ,  Hong Yu ,  Wei Hong

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening. A second material layer is formed over the first material layer on the exposed upper portions of the first material layer in the second opening. An intermix layer is formed in the second opening using the first and second material layers. The protective layer from the second opening is removed to expose the first material layer.

公开(公告)号：US11004748B2

公开(公告)日：2021-05-11

申请号：US16432899

申请日：2019-06-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L27/088

Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.

公开(公告)号：US11002763B2

公开(公告)日：2021-05-11

申请号：US16100297

申请日：2018-08-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ye Wang ,  Hanyi Ding ,  Timothy M. Platt

IPC: G01R1/073 ,  G01R1/067

Abstract: Embodiments of the disclosure provide a probe structured for electrical and photonics testing of a photonic integrated circuit (PIC) die, the probe including: a membrane having a first surface and an opposing second surface and including conductive traces, the membrane being configured for electrical coupling to a probe interface board (PIB); a set of probe tips positioned on the membrane, the set of probe tips being configured to send electrical test signals to the PIC die or receive electrical test signals from the PIC die; and a photonic test assembly disposed on the membrane and electrically coupled to the conductive traces of the membrane, the photonic test assembly positioned for substantial alignment with a photonic I/O element of the PIC die, wherein the photonic test assembly is configured to transmit a photonic input signal to the photonic I/O element or detect a photonic output signal from the photonic I/O element.

公开(公告)号：US20210134881A1

公开(公告)日：2021-05-06

申请号：US16668092

申请日：2019-10-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anuj Gupta ,  Bipul C. Paul

IPC: H01L27/22 ,  H01L23/528 ,  H01L23/522

Abstract: One illustrative device includes an array of memory cells including a first row of memory cells and a second row of memory cells adjacent the first row, a first gate structure extending along the first row, a second gate structure extending along the second row, a first wordline positioned in a first layer above the array and contacting the first gate structure, and a second wordline positioned in a second layer above the first layer and contacting the second gate structure, wherein the second wordline vertically overlaps the first wordline.

公开(公告)号：US20210126086A1

公开(公告)日：2021-04-29

申请号：US16667037

申请日：2019-10-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Lili Cheng ,  Robert J. Fox, III ,  Luke England

IPC: H01L49/02

Abstract: Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.

公开(公告)号：US20210125984A1

公开(公告)日：2021-04-29

申请号：US16660868

申请日：2019-10-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Jiehui Shu

IPC: H01L27/092 ,  H01L21/8238

Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layer. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.

公开(公告)号：US20210124272A1

公开(公告)日：2021-04-29

申请号：US16661220

申请日：2019-10-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ezra D.B. Hall ,  Jed H. Rankin ,  Alok Vaid

IPC: G03F7/20

Abstract: Embodiments of the present disclosure provide an apparatus including mask pattern formed on a mask substrate. A plurality of spatial radiation modulators may be vertically displaced from the mask pattern, and distributed across a two-dimensional area. Each of the plurality of spatial radiation modulators may be adjustable between a first transparent state and a second transparent state to control whether radiation transmitted through the mask pattern passes through each of the plurality of spatial radiation modulators.