公开(公告)号：US12170124B2

公开(公告)日：2024-12-17

申请号：US17692262

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Yoav Weinberg

IPC: G11C29/50 ,  G11C29/02

Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.

公开(公告)号：US12170113B2

公开(公告)日：2024-12-17

申请号：US18076488

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Akira Goda ,  Jonathan S. Parry ,  Violante Moschiano

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/28

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

公开(公告)号：US12169648B2

公开(公告)日：2024-12-17

申请号：US17888325

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry ,  Nitul Gohain

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

公开(公告)号：US20240414911A1

公开(公告)日：2024-12-12

申请号：US18808256

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H10B12/00

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

公开(公告)号：US20240413841A1

公开(公告)日：2024-12-12

申请号：US18738499

申请日：2024-06-10

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Toby D. Robbs

IPC: H03M13/11 ,  H03M13/00

Abstract: Apparatuses and methods for on-device error correction implemented in a memory. A memory may have a first column plane comprising a first number of bit lines and a parity column plane that has a second number of parity bit lines in which the first number is different than the second number. In an access operation, a column select signal may activate the first number of bit lines in the first column plane and the second number of parity bit lines in the second column plane.

公开(公告)号：US20240412805A1

公开(公告)日：2024-12-12

申请号：US18808418

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Angelo Alberto Rovelli ,  Craig A. Jones

IPC: G11C29/52 ,  G11C29/02

Abstract: A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

公开(公告)号：US20240411459A1

公开(公告)日：2024-12-12

申请号：US18811658

申请日：2024-08-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Jonathan S. Parry ,  Sivagnanam Parthasarathy ,  Akira Goda

IPC: G06F3/06

Abstract: A method includes determining a logical saturation of a memory device in a memory sub-system and adjusting a code rate of the memory device based on the logical saturation, wherein the code rate represents a ratio of user data to a combination of the user data and error correction data.

公开(公告)号：US20240411449A1

公开(公告)日：2024-12-12

申请号：US18646266

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Tomer Tzvi Eliash ,  Zhenming Zhou

IPC: G06F3/06

Abstract: A processing device, operatively coupled with a memory device, performs a first sequence of programming operations on a first set of cells addressable by a first wordline of the memory device. The processing device identifies a second wordline of the memory device, wherein a second physical location of the second wordline is in a predefined relationship with a first physical location of the first wordline. The processing device performs a second sequence of programming operations on a second set of cells addressable by the second wordline of the first die, wherein a first order of the first sequence of programming operations is different from a second order of the second sequence of programming operations.

公开(公告)号：US12167586B2

公开(公告)日：2024-12-10

申请号：US17460156

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani

IPC: H10B12/00 ,  G11C11/22 ,  H10B53/10 ,  H10B53/30

Abstract: Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

公开(公告)号：US12166094B2

公开(公告)日：2024-12-10

申请号：US17373258

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Richard J. Hill ,  Indra V. Chary ,  Lars P. Heineck

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/528 ,  H01L29/40

Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.