公开(公告)号：US20060054954A1

公开(公告)日：2006-03-16

申请号：US11223796

申请日：2005-09-08

Applicant: Antonello Santangelo ,  Salvatore Cascino ,  Leonardo Gervasi

Inventor： Antonello Santangelo ,  Salvatore Cascino ,  Leonardo Gervasi

IPC: H01L29/94

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66659

Abstract: A lateral MOS device is formed in a body having a surface and is formed by a semiconductor layer of a first conductivity type; a drain region of a second conductivity type, formed in the semiconductor layer and facing the surface; a source region of the second conductivity type, formed in the semiconductor layer and facing the surface; a channel of the first conductivity type, formed in the semiconductor layer between the drain region and the source region and facing the surface; and an insulated gate region, formed on top of the surface over the channel region. In order to improve the dynamic performance, a conductive region extends only on one side of the insulated gate region, on top of the drain region but not on top of the insulated gate region.

Abstract translation: 横向MOS器件形成在具有表面的主体中并且由第一导电类型的半导体层形成; 形成在半导体层中并面向表面的第二导电类型的漏极区; 形成在半导体层中并面向表面的第二导电类型的源极区; 第一导电类型的沟道，形成在漏极区域和源极区域之间并面向表面的半导体层中; 以及形成在通道区域上的表面的顶部上的绝缘栅极区域。 为了提高动态性能，导电区域仅在绝缘栅极区域的一侧上在漏极区域的顶部延伸，而不在绝缘栅极区域的顶部上延伸。

公开(公告)号：US20060034592A1

公开(公告)日：2006-02-16

申请号：US10918658

申请日：2004-08-12

Applicant: Giuseppe Maiocchi ,  Roberto Oboe ,  Federico Marcassa

Inventor： Giuseppe Maiocchi ,  Roberto Oboe ,  Federico Marcassa

IPC: H02P7/68

CPC classification number: H02P7/28 ,  G11B5/5547

Abstract: A method for controlling in an open-loop voltage mode a DC motor driven through a power amplifier includes generating a control voltage for the DC motor to be input to the power amplifier based upon a difference between an external command and a correction signal, and amplifying the control voltage for generating a replica of an output of the power amplifier. A model of the DC motor is defined based upon electrical parameters of the DC motor. The method further includes estimating current flowing in the DC motor based upon the replica of the output of the power amplifier and the model of the DC motor, and generating the correction signal proportional to the estimated current.

公开(公告)号：US20060020653A1

公开(公告)日：2006-01-26

申请号：US11179027

申请日：2005-07-11

Applicant: Daniele Lo Iacono ,  Marco Ronchi

Inventor： Daniele Lo Iacono ,  Marco Ronchi

IPC: G06F7/38

CPC classification number: G06F7/5332 ,  G06F7/4824 ,  G06F7/49994 ,  G06F7/508 ,  H03M7/04

Abstract: A system, such as, e.g., a multiplier, for processing digital signals by using digital signals in the Canonic Signed Digit representation, the system including an input element to make the digital signals available in the Binary Canonic Signed Digit representation, a converter to convert the digital signals into Canonic Signed Digit representation for use in processing. The input element may be a memory where the signals are stored in the Binary Canonic Signed Digit representation. Alternatively, the input element is adapted to be fed with digital signals in the two's complement representation, and includes at least one converter to convert the digital signals from the two's complement representation into the Binary Canonic Signed Digit representation. This preferably occurs via the T2I transformation, which leads to generating signals in the Canonic Signed Digit representation, which are then converted to the Binary Canonic Signed Digit representation.

Abstract translation: 一种系统，例如乘法器，用于通过在加农生物签名数字表示中使用数字信号来处理数字信号，该系统包括用于使二进制加拿大签名数字表示中的数字信号可用的输入元件，转换器 数字信号转换成Canonic Signed Digit表示用于处理。 输入元件可以是其中信号被存储在二进制加拿大签名数字表示中的存储器。 或者，输入元件适于以二进制补码表示中的数字信号馈送，并且包括至少一个转换器，用于将来自二进制补码表示的数字信号转换为二进制加法符号数字表示。 这优选地通过T2I变换发生，这导致在加农声有符号数字表示中产生信号，然后将其转换为二进制加法符号数字表示。

公开(公告)号：US20060017131A9

公开(公告)日：2006-01-26

申请号：US10327702

申请日：2002-12-20

Applicant: Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

Inventor： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

IPC: H01L29/00

CPC classification number: H01L21/76283 ,  H01L21/3003 ,  H01L21/3247 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0649 ,  Y10S438/967

Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.

公开(公告)号：US20060001474A1

公开(公告)日：2006-01-05

申请号：US11159976

申请日：2005-06-23

Applicant: Diego Armaroli ,  Davide Betta ,  Marco Ferrari

Inventor： Diego Armaroli ,  Davide Betta ,  Marco Ferrari

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: The method controls a charge pump generator having at least an output tank capacitor on which a regulated output voltage of the generator is produced, and a pump capacitor that is connected to a supply node and to ground during charge phases and is coupled in an anti-parallel configuration to the output tank capacitor during charge transfer phases, alternated to the charge phases. The method limits the current absorbed from the supply because the transfer capacitor is charged during at least an initial charge phase with a constant charge current of a pre-established value.

Abstract translation: 该方法控制电荷泵发生器，该电荷泵发生器至少具有产生发电机的调节输出电压的输出电容器电容器，以及在充电阶段连接到电源节点并接地的泵电容器， 在电荷转移阶段，并联配置到输出槽电容器，交替进入充电阶段。 该方法限制了从电源吸收的电流，因为传输电容器在至少初始充电阶段被充电，具有预定值的恒定充电电流。

公开(公告)号：US20050232019A1

公开(公告)日：2005-10-20

申请号：US11093012

申请日：2005-03-29

Applicant: Giovanni Vorraro ,  Paolo Villani

Inventor： Giovanni Vorraro ,  Paolo Villani

IPC: G11C11/34 ,  G11C16/34 ,  G11C29/00

CPC classification number: G11C16/3454

Abstract: A sequential program-verify method is used in a non-volatile memory device including a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments. The method includes the steps of: writing a set of target values into a plurality of blocks of cells, the corresponding cells of each block belonging to a common alignment, verifying each block of cells in succession to assert a fault value for each alignment in response to a non-compliance of the value stored in the cell of the block belonging to the alignment with the corresponding target value, buffering the fault values, and in response to the verification of all the blocks of cells providing an indication of the alignments being defective according to tpe fault values.

Abstract translation: 在包括多个存储单元的非易失性存储器件中使用顺序程序验证方法，每个存储器单元用于存储逻辑值，所述单元被布置成多个对准。 该方法包括以下步骤：将一组目标值写入到多个单元块中，每个块的相应单元属于公共对准，连续验证每个单元块以响应每个对齐的故障值 存储在属于与对应目标值的对齐的块的小区中的值的不一致，缓冲故障值，以及响应于提供对齐缺陷的指示的所有小区块的验证 根据tpe故障值。

公开(公告)号：US20050186780A1

公开(公告)日：2005-08-25

申请号：US11009687

申请日：2004-12-10

Applicant: Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

Inventor： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76838

Abstract: The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

Abstract translation: 该方法防止半导体器件中的导电互连结构的氧化或污染现象，并且包括在基底层上提供半导体层或氧化物层，导电层或叠层，以及导电层或叠层上的抗反射涂层（ARC）层。 该方法在抗反射涂层上提供薄的电介质覆盖层，以填充或覆盖存在于抗反射涂层中的微裂缝。

公开(公告)号：US20050127982A1

公开(公告)日：2005-06-16

申请号：US10982528

申请日：2004-11-05

Applicant: Osama Khouri ,  Giancarlo Ragone

Inventor： Osama Khouri ,  Giancarlo Ragone

IPC: G05F1/10 ,  H02M3/07

CPC classification number: H02M3/073

Abstract: A circuit for converting a direct current input voltage into an output voltage greater than the input voltage. The circuit includes a charge pump and a block for generating pulse signals of a predetermined frequency to be applied to a control input of the charge pump. The settling time, i.e. the time necessary for the output voltage to attain its operating value and to maintain it with a given precision, is reduced by providing the circuit with charge injection control via modulation of the duty cycle of the pulse signals as a function of the difference between the output voltage, or a predetermined fraction thereof, and a predetermined reference voltage and in such a manner as to reduce the settling time as the difference diminishes. The circuit includes a regulator that controls the charge pump based upon the predetermined reference voltage.

Abstract translation: 用于将直流输入电压转换成大于输入电压的输出电压的电路。 该电路包括一个电荷泵和用于产生预定频率的脉冲信号以供应给电荷泵的控制输入的块。 通过调节脉冲信号的占空比来调节电路的电荷注入控制，降低了稳定时间，即输出电压达到其工作值并保持给定精度所需的时间，作为 输出电压或其预定分数之间的差异与预定参考电压之间的差异，并且以随着差异减小而减小稳定时间的方式。 电路包括基于预定参考电压来控制电荷泵的调节器。

公开(公告)号：US20050046973A1

公开(公告)日：2005-03-03

申请号：US10895012

申请日：2004-07-19

Applicant: Pierangelo Magni ,  Remi Brechignac ,  Chek Kho ,  Kum Weng Loo

Inventor： Pierangelo Magni ,  Remi Brechignac ,  Chek Kho ,  Kum Weng Loo

IPC: G02B7/02 ,  G02B27/62 ,  H04N5/225

CPC classification number: G02B13/001 ,  G02B7/02 ,  G02B27/62 ,  H01L2224/48227 ,  H04N5/2254

Abstract: A method is described for fixing a lens of an optical group with respect to an optical sensor in an image acquisition device comprising the steps of housing the optical sensor in a housing, fixing a lower holder of the optical group to the housing, aligning an upper holder of the optical group, wherein the lens is placed, with the sensor so as to align a focusing point of the lens with respect to the sensor, welding the upper holder to the lower holder. The welding step may be performed by means of ultrasounds.

Abstract translation: 描述了一种用于在图像采集装置中固定相对于光学传感器的光学组的透镜的方法，包括以下步骤：将光学传感器容纳在壳体中，将光学组的下部固定器固定到壳体上， 将光学组的保持器放置在传感器上，以便使透镜的聚焦点相对于传感器对准，将上支架焊接到下支架。 焊接步骤可以通过超声波进行。

公开(公告)号：US20050030316A1

公开(公告)日：2005-02-10

申请号：US10886528

申请日：2004-07-07

Applicant: Daniele Sirtori ,  Danilo Pau ,  Pierluigi Gardella ,  Massimiliano Barone ,  Mirko Falchetto

Inventor： Daniele Sirtori ,  Danilo Pau ,  Pierluigi Gardella ,  Massimiliano Barone ,  Mirko Falchetto

IPC: G06T15/00 ,  G09G5/397 ,  H04N7/26 ,  H04N7/46 ,  G09G5/00 ,  H03L7/00 ,  H04N5/14 ,  H04N7/12 ,  H04N7/14

CPC classification number: G06T15/005 ,  G06T9/001 ,  H04N19/29 ,  H04N19/31 ,  H04N19/42 ,  H04N19/517 ,  H04N19/537 ,  H04N19/577 ,  H04N19/587

Abstract: A graphic system includes a pipelined graphic engine for generating image frames for display. The pipelined graphic engine includes a geometric processing stage for performing motion extraction, and a rendering stage for generating full image frames at a first frame rate for display at a second frame rate. The second frame rate is higher than the first frame rate. A motion encoder stage receives motion information from the geometric processing stage, and produces an interpolated frame signal representative of interpolated frames. A motion compensation stage receives the interpolated frame signal from the motion encoder stage, and the full image frames from the rendering stage for generating the interpolated frames. A preferred application is in graphic systems that operate in association with smart displays through a wireless connection, such as in mobile phones.

Abstract translation: 图形系统包括用于生成用于显示的图像帧的流水线图形引擎。 流水线图形引擎包括用于执行运动提取的几何处理级，以及用于以第一帧速率生成全图像帧以用于以第二帧速率显示的渲染级。 第二帧率高于第一帧速率。 运动编码器级接收来自几何处理级的运动信息，并产生代表内插帧的内插帧信号。 运动补偿级从运动编码器级接收内插帧信号，并从渲染级接收用于产生内插帧的全图像帧。 优选的应用是在通过无线连接（例如在移动电话中）与智能显示器相关联的图形系统中。