公开(公告)号：US20230031595A1

公开(公告)日：2023-02-02

申请号：US17961613

申请日：2022-10-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JAMES R. MAGRO ,  KEDARNATH BALAKRISHNAN ,  BRENDAN T. MANGAN

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02 ,  G06F12/1009

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

公开(公告)号：US20230030679A1

公开(公告)日：2023-02-02

申请号：US17386115

申请日：2021-07-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  John Kalamatianos ,  Gagandeep Panwar

IPC: G06F12/02 ,  G06F12/0817 ,  G06F12/06 ,  G06F9/30

Abstract: A technical solution to the technical problem of how to improve dispatch throughput for memory-centric commands bypasses address checking for certain memory-centric commands. Implementations include using an Address Check Bypass (ACB) bit to specify whether address checking should be performed for a memory-centric command. ACB bit values are specified in memory-centric instructions, automatically specified by a process, such as a compiler, or by host hardware, such as dispatch hardware, based upon whether a memory-centric command explicitly references memory. Implementations include bypassing, i.e., not performing, address checking for memory-centric commands that do not access memory and also for memory-centric commands that do access memory, but that have the same physical address as a prior memory-centric command that explicitly accessed memory to ensure that any data in caches was flushed to memory and/or invalidated.

公开(公告)号：US11567554B2

公开(公告)日：2023-01-31

申请号：US15837918

申请日：2017-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jay Fleischman ,  Michael Estlick ,  Michael Christopher Sedmak ,  Erik Swanson ,  Sneha V. Desai

IPC: G06F1/32 ,  G06F1/324 ,  G06F9/38 ,  G06F13/38 ,  G06F9/30

Abstract: A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.

公开(公告)号：US20230024130A1

公开(公告)日：2023-01-26

申请号：US17564166

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh ACHARYA ,  Sreekanth GODEY ,  Ruijin WU

IPC: G06F9/50

Abstract: A processing unit is configured differently based on an identified workload, and each configuration of the processing unit is exposed to software (e.g., to a device driver) as a different virtual processing unit. Using these techniques, a processing system is able to provide different configurations of the processing unit to support different types of workloads, thereby conserving system resources. Further, by exposing the different configurations as different virtual processing units, the processing system is able to use existing device drivers or other system infrastructure to implement the different processing unit configurations.

公开(公告)号：US11562459B2

公开(公告)日：2023-01-24

申请号：US17128388

申请日：2020-12-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Noor Mohammed Saleem Bijapur ,  Ashish Khandelwal ,  Laurent Lefebvre ,  Anirudh R. Acharya

IPC: G06F12/0804 ,  G06T1/60 ,  G06T1/20 ,  G06F12/0888 ,  G06F12/0806 ,  G09G5/39

Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

公开(公告)号：US20230014520A1

公开(公告)日：2023-01-19

申请号：US17379362

申请日：2021-07-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ROTO LE

IPC: G06T11/00 ,  G06K9/32

Abstract: Content feedback based on region of view, including: determining, for a user of a recipient device receiving content from a presenting device, a region of view of the content associated with the user; generating, based on the region of view, a visual overlay; and displaying, by the presenting device, the visual overlay applied to the content.

公开(公告)号：US11558592B1

公开(公告)日：2023-01-17

申请号：US17558459

申请日：2021-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Linwei Yu ,  Yang Ling ,  Jiangli Ye

IPC: H04N9/64 ,  H04N5/232 ,  H04N9/04

Abstract: Devices, methods, and systems for detecting false color in an image. An edge preserving filter is applied to an image sensor output to generate a first demosaiced image. A low pass filter is applied to the image sensor output to generate a second demosaiced image. A hue difference between the first demosaiced image and the second demosaiced image is calculated. A false color region is detected responsive to the hue difference exceeding a threshold hue difference.

公开(公告)号：US11556162B2

公开(公告)日：2023-01-17

申请号：US15923153

申请日：2018-03-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Shijia Wei ,  Joseph L. Greathouse ,  John Kalamatianos

IPC: G06F1/32 ,  G06F9/38 ,  G06F11/36

Abstract: A processor utilizes instruction based sampling to generate sampling data sampled on a per instruction basis during execution of an instruction. The sampling data indicates what processor hardware was used due to the execution of the instruction. Software receives the sampling data and generates an estimate of energy used by the instruction based on the sampling data. The sampling data may include microarchitectural events and the energy estimate utilizes a base energy amount corresponding to the instruction executed along with energy amounts corresponding to the microarchitectural events in the sampling data. The sampling data may include switching events associated with hardware blocks that switched due to execution of the instruction and the energy estimate for the instruction is based on the switching events and capacitance estimates associated with the hardware blocks.

公开(公告)号：US20230009881A1

公开(公告)日：2023-01-12

申请号：US17371459

申请日：2021-07-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Eric J. Chapman ,  Alan D. Smith ,  Edward Chang

IPC: G06F1/28

Abstract: A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.

公开(公告)号：US20230004400A1

公开(公告)日：2023-01-05

申请号：US17943265

申请日：2022-09-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JYOTI RAHEJA ,  HIDEKI KANAYAMA ,  GUHAN KRISHNAN ,  RUIHUA PENG

IPC: G06F9/4401 ,  G06F1/3234 ,  G06F12/0804 ,  G06F1/3287

Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.