公开(公告)号：US20240403177A1

公开(公告)日：2024-12-05

申请号：US18678557

申请日：2024-05-30

Applicant: Micron Technology, Inc.

Inventor： Su Wei Lim ,  Senthil Murugan Thangaraj ,  Marco Sforzin ,  Daniele Balluchi ,  Massimiliano Patriarca ,  Giorgio Servalli ,  Angelo Visconti ,  Antonino Capri’ ,  Garth N. Grubb ,  Amitava Majumdar ,  Miguel Mares

IPC: G06F11/20 ,  G06F11/14

Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

公开(公告)号：US20240402946A1

公开(公告)日：2024-12-05

申请号：US18680608

申请日：2024-05-31

Applicant: Micron Technology, Inc.

Inventor： Manik Advani ,  Tomoko Ogura Iwasaki

IPC: G06F3/06

Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys and a value data block. The memory system further includes a processing device that receives an input search key and identifies one of the plurality of stored search keys that matches the input search key, the one of the plurality of stored search keys having an associated match location in the CAM block. The processing device further determines, using the associated match location, a corresponding value location in the value data block and retrieves, from the value location in the value data block, data representing a value associated with the input search key.

公开(公告)号：US20240402922A1

公开(公告)日：2024-12-05

申请号：US18806444

申请日：2024-08-15

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

IPC: G06F3/06

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

公开(公告)号：US12159219B2

公开(公告)日：2024-12-03

申请号：US16997599

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Richard C. Murphy

IPC: G06N3/063 ,  G06F7/544 ,  G06F7/57 ,  G06F9/30 ,  G06F9/50 ,  G06N3/045 ,  G06N3/049 ,  G06N3/065 ,  G06N3/08 ,  G11C11/34 ,  G11C11/54

Abstract: Systems, apparatuses, and methods related to a neuron using posits are described. An example apparatus may include a memory array including a plurality of memory cells configured to store data. The data can include a plurality of bit strings. The example apparatus may include a neuron component coupled to the memory array. The neuron component can include neuron circuitry configured to perform neuromorphic operations on at least one of the plurality of bit strings.

公开(公告)号：US12158840B2

公开(公告)日：2024-12-03

申请号：US18512850

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： David A. Roberts

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16

Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.

公开(公告)号：US12158792B2

公开(公告)日：2024-12-03

申请号：US17740188

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: G06F1/3234 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F11/00 ,  G06F11/30 ,  G06F11/34

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US20240395349A1

公开(公告)日：2024-11-28

申请号：US18667358

申请日：2024-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshinori Fujiwara ,  Kenji Yoshida

IPC: G11C29/46 ,  G11C29/00 ,  G11C29/24

Abstract: Apparatuses and methods for forcing memory cell failures in a memory device are disclosed. An example apparatus includes a column disable control circuit coupled to a plurality of column latch sets to receive match signals and associated column plane addresses, the column disable control circuit configured to provide redundant column select signals and column plane masking signals based on the match signals and associated column plane addresses, the column disable control circuit further configured to provide the redundant column select signal and the column plane masking signal corresponding to an active match signal and associated column plane address from a designated column latch set when a disable memory test mode is enabled to cause one or more memory cells of main memory to fail.

公开(公告)号：US20240395326A1

公开(公告)日：2024-11-28

申请号：US18652288

申请日：2024-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Paolo Tessariol ,  Richard J. Hill ,  Aaron S. Yip ,  Kunal Parekh

IPC: G11C16/04 ,  G11C5/06 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Memory array structures might include a data line, a common source, and a plurality of sub-blocks of memory cells selectively connected to the data line and to the common source. Sub-blocks of memory cells might include memory cells formed to be around channel material structures, and might include isolation of source-side select lines of adjacent sub-blocks of memory cells. Methods are included for forming such memory array structures.

公开(公告)号：US20240395303A1

公开(公告)日：2024-11-28

申请号：US18794453

申请日：2024-08-05

Applicant: Micron Technology, Inc.

Inventor： Si Hong Kim ,  John D. Porter

IPC: G11C11/22

Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.

公开(公告)号：US20240394164A1

公开(公告)日：2024-11-28

申请号：US18696218

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Ziqing WU ,  Wenjun WU ,  Xiaolai ZHU ,  Chunyu SHENG ,  Xiao WANG

IPC: G06F11/30 ,  G06F11/34

Abstract: Methods, systems, and devices for memory performance evaluation using address mapping information are described. A memory system may write a data file associated with a range of logical block addresses to a first set of blocks in a set of memory dies. The memory system may then determine, for a memory die of the set of memory dies that stores a portion of the data file, a quantity of read operations for reading the portion of the data file. The memory system may determine the quantity of read operations based on address mapping information that maps logical block addresses associated with the datafile to physical addresses. After determining the quantity of read operations, the memory device may use the quantity of read operations to determine a performance metric associated with the data file and the first set of blocks.