公开(公告)号：US20190244669A1

公开(公告)日：2019-08-08

申请号：US16387377

申请日：2019-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US10373686B2

公开(公告)日：2019-08-06

申请号：US15660552

申请日：2017-07-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC: H01L25/00 ,  G11C16/08 ,  G11C7/10 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.

公开(公告)号：US10311958B2

公开(公告)日：2019-06-04

申请号：US15593231

申请日：2017-05-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: H01L27/115 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US10297327B2

公开(公告)日：2019-05-21

申请号：US15952155

申请日：2018-04-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/08 ,  G11C7/06 ,  G11C8/08 ,  G11C16/10 ,  G11C16/28 ,  H01L27/112 ,  H01L27/11582 ,  H01L49/02

Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.

公开(公告)号：US20190121556A1

公开(公告)日：2019-04-25

申请号：US16228313

申请日：2018-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/04 ,  H01L21/78 ,  H01L23/00 ,  H01L29/423 ,  G11C16/10 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/08 ,  G11C16/34

Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

公开(公告)号：US10269432B2

公开(公告)日：2019-04-23

申请号：US15479235

申请日：2017-04-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US20190114097A1

公开(公告)日：2019-04-18

申请号：US15784025

申请日：2017-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  H01L29/423 ,  H01L23/00 ,  H01L21/78 ,  G11C16/04 ,  H01L27/11521

Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

公开(公告)号：US20180047454A1

公开(公告)日：2018-02-15

申请号：US15792590

申请日：2017-10-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Vipin Tiwari

IPC: G11C16/28 ,  G11C16/06 ,  G11C16/24 ,  G11C16/00

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063 ,  H01L27/11519

Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.

公开(公告)号：US20170358360A1

公开(公告)日：2017-12-14

申请号：US15687191

申请日：2017-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/12 ,  G11C16/24 ,  G11C16/10 ,  G11C16/08 ,  G11C16/30

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

公开(公告)号：US20170345840A1

公开(公告)日：2017-11-30

申请号：US15489548

申请日：2017-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11568 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8238

CPC classification number: H01L27/11568 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/823821 ,  H01L28/00

Abstract: A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.