公开(公告)号：US20180088155A1

公开(公告)日：2018-03-29

申请号：US15708958

申请日：2017-09-19

Applicant: Analog Devices Global Unlimited Company

Inventor： David J. Clarke ,  Stephen Denis Heffernan ,  Alan J. O'Donnell ,  Patrick M. McGuinness

IPC: G01R19/165 ,  H01L23/62 ,  H01L23/525 ,  G01N25/04 ,  G01R31/28

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

公开(公告)号：US20180076782A1

公开(公告)日：2018-03-15

申请号：US15264432

申请日：2016-09-13

Applicant: Analog Devices Global

Inventor： Andreas Koch

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45 ,  H03F3/45941 ,  H03F2200/261 ,  H03F2200/481 ,  H03F2203/45101 ,  H03F2203/45138 ,  H03F2203/45424 ,  H03F2203/45426 ,  H03F2203/45586

Abstract: Apparatus and methods for a difference amplifier are provided. In certain examples, the difference amplifier can provide high common mode rejection without differential signal attenuation. In an example, a difference amplifier circuit can include first and second amplifiers, first and second buffer amplifiers, a first feedback voltage divider coupled between an output of the first buffer amplifier and an output of the second amplifier, and a second feedback voltage divider coupled between an output of the second buffer amplifier and an output of the first amplifier.

公开(公告)号：US20180076779A1

公开(公告)日：2018-03-15

申请号：US15600484

申请日：2017-05-19

Applicant: Analog Devices Global

Inventor： Hanqing Wang ,  Gerard Mora-Puchalt

IPC: H03F3/00 ,  H03F3/42 ,  H03F3/45 ,  H03F3/393 ,  H03F1/02 ,  H03F1/56 ,  H03F1/32

CPC classification number: H03F3/005 ,  H03F1/02 ,  H03F1/14 ,  H03F1/3211 ,  H03F1/56 ,  H03F3/387 ,  H03F3/393 ,  H03F3/426 ,  H03F3/45071 ,  H03F3/45475 ,  H03F2200/213 ,  H03F2200/267 ,  H03F2200/271 ,  H03F2200/378 ,  H03F2203/45458 ,  H03F2203/45514 ,  H03M3/00 ,  H03M3/496

Abstract: A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.

公开(公告)号：US09912342B2

公开(公告)日：2018-03-06

申请号：US15369175

申请日：2016-12-05

Applicant: Analog Devices Global

Inventor： Zhao Li ,  Hajime Shibata ,  Trevor Clifford Caldwell ,  Yunzhi Dong ,  Jialin Zhao ,  Richard E. Schreier ,  Victor Kozlov ,  David Nelson Alldred ,  Prawal Man Shrestha

IPC: H03M1/10 ,  H03M1/34 ,  H03M1/12 ,  H03M1/06 ,  H03M3/00

CPC classification number: H03M1/1009 ,  H03M1/0626 ,  H03M1/066 ,  H03M1/1245 ,  H03M1/34 ,  H03M3/388 ,  H03M3/422

Abstract: An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.

公开(公告)号：US09893623B2

公开(公告)日：2018-02-13

申请号：US14719945

申请日：2015-05-22

Applicant: Analog Devices Global

Inventor： Hirohisa Tanabe

IPC: H02M3/158

CPC classification number: H02M3/1582

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p−p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p−p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

公开(公告)号：US09887687B2

公开(公告)日：2018-02-06

申请号：US14608072

申请日：2015-01-28

Applicant: Analog Devices Global

Inventor： Seamus Paul Whiston ,  Bernard Patrick Stenson ,  Michael Noel Morrissey ,  Michael John Flynn

IPC: H05K3/30 ,  H05K1/18 ,  H03H9/17 ,  H03H9/46 ,  H03H9/22 ,  H03H9/15 ,  H03H9/24 ,  H03H9/02

CPC classification number: H03H9/462 ,  H01L2224/48227 ,  H03H9/174 ,  H03H9/22 ,  H03H2009/02165 ,  H03H2009/155 ,  H03H2009/2421

Abstract: A method of trimming a component is provided in which the component is protected from oxidation or changes in stress after trimming. As part of the method, a protective glass cover is bonded to the surface of a semiconductor substrate prior to trimming (e.g., laser trimming) of a component. This can protect the component from oxidation after trimming, which may change its value or a parameter of the component. It can also protect the component from changes in stress acting on it or on the die adjacent it during packaging, which may also change a value or parameter of the component.

公开(公告)号：US09866110B2

公开(公告)日：2018-01-09

申请号：US14469975

申请日：2014-08-27

Applicant: Analog Devices Global

Inventor： Miguel A. Ruiz ,  Jose Tejada Gomez

IPC: H02M3/07 ,  G05F1/618

CPC classification number: H02M3/07 ,  G05F1/618

Abstract: A switched capacitor voltage converter is provided that includes an array of switches configured to alternately switch multiple capacitors between a charge configuration in which the multiple capacitors are coupled in series with each other and in parallel with the source voltage and a discharge configuration in which a first set of capacitors having n capacitors are coupled in parallel with each other and in series with the load and a second set of capacitors having m capacitors coupled in parallel with the load.

公开(公告)号：US09864389B1

公开(公告)日：2018-01-09

申请号：US15348420

申请日：2016-11-10

Applicant: Analog Devices Global

Inventor： Sharad Vijaykumar

IPC: G05F3/30 ,  G05F1/575

CPC classification number: G05F1/575

Abstract: A delta-Vbe based bandgap reference voltage circuit generates a temperature stable reference voltage. First and second paths of the circuit each include a respective transistor coupled in series with a resistance. The collector current density of the transistor in first path is lower than the collector current density of transistor in the other path. A control path is used to generate a 2Vbe voltage that is coupled to the base nodes of the resistors in each path. A resistance that is coupled between a common node of a first end of the two paths and a circuit ground node. The circuit current is controlled by this resistance and a voltage drop of 2ΔVbe is across the resistance. The output reference voltage of the circuit is 2(Vbe+ΔVbe) when stack resistors in each path are used.

公开(公告)号：US20170356934A1

公开(公告)日：2017-12-14

申请号：US15179249

申请日：2016-06-10

Applicant: Analog Devices Global

Inventor： Jonathan Ephraim David Hurwitz ,  David S. Yaney ,  Petre Minciunescu ,  David P. Smith

IPC: G01R15/18 ,  G01R19/00

CPC classification number: G01R15/181 ,  G01R19/0092

Abstract: The present disclosure provides an improved Rogowski-type current sensor. In order to allow the sensing coil and the compensation wire to overlap, the sensor is produced using two boards. The current sensing coil is provided on one board, and the compensation wire is provided on another board. The coil and the wire are arranged such that they at least partially overlap, and ideally the compensation wire is formed entirely within the area defined by the coil, albeit in a different plane. This arrangement makes the current sensor far better at rejecting interference than prior art PCB arrangements. In addition, the coil may be formed on a two-sided board. The board has upper radial elements formed on an upper surface, and lower radial elements formed on lower surface. The radial elements are connected using vias formed in the board. The upper radial elements are arranged in a first plane, and the lower radial elements are formed in a second parallel plane. The upper radial elements are arranged so that they are aligned with the lower radial elements, such that a pair of radial elements form a radial plane that is perpendicular to the board surface. This symmetry ensures excellent sensitivity to currents in a conductor.

公开(公告)号：US09838031B2

公开(公告)日：2017-12-05

申请号：US15360984

申请日：2016-11-23

Applicant: Analog Devices Global

Inventor： Yunzhi Dong ,  Hajime Shibata ,  Trevor Clifford Caldwell ,  Zhao Li ,  Jialin Zhao ,  Jose Barreiro Silva

IPC: H03M3/00 ,  H03M1/36

CPC classification number: H03M3/422 ,  H03M1/361 ,  H03M3/322 ,  H03M3/344 ,  H03M3/378 ,  H03M3/388 ,  H03M3/414 ,  H03M3/436 ,  H03M3/464

Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.