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    LOW POWER HALF-VDD GENERATION CIRCUIT WITH HIGH DRIVING CAPABILITY
    2.
    发明申请
    LOW POWER HALF-VDD GENERATION CIRCUIT WITH HIGH DRIVING CAPABILITY 审中-公开

    公开(公告)号：US20190317541A1

    公开(公告)日：2019-10-17

    申请号：US15951894

    申请日：2018-04-12

    Applicant: Analog Devices Global Unlimited Company

    Inventor： Hanqing Wang ,  Gerard Mora-Puchalt

    IPC: G05F3/16 ,  H03K17/687 ,  H03F3/45 ,  H03F3/00

    Abstract: A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.

    Fast settling capacitive gain amplifier circuit
    3.
    发明授权
    Fast settling capacitive gain amplifier circuit 有权

    公开(公告)号：US10044327B2

    公开(公告)日：2018-08-07

    申请号：US15600484

    申请日：2017-05-19

    Applicant: Analog Devices Global

    Inventor： Hanqing Wang ,  Gerard Mora-Puchalt

    IPC: H03F3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F1/56 ,  H03F3/393 ,  H03F3/42 ,  H03F3/45 ,  H03F1/14 ,  H03F3/387 ,  H03M3/00

    Abstract: A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.

    Operational amplifier
    4.
    发明授权
    Operational amplifier 有权

    公开(公告)号：US10116268B2

    公开(公告)日：2018-10-30

    申请号：US15401522

    申请日：2017-01-09

    Applicant: Analog Devices Global

    Inventor： Sharad Vijaykumar ,  Gerard Mora-Puchalt

    IPC: H03F1/30 ,  H03F1/26 ,  H03F3/45

    Abstract: The amplifier circuit includes a pair of differential input stages coupled to an output stage where both a selected input stage and an unselected input stage are active with one of either a differential input signal or a reference voltage. A switching network couples a first input differential signal to a first differential input stage and a reference voltage to a second differential input stage when an amplifier input signal is less than a threshold voltage. The switching circuit also couples the second input differential signal to the second differential input stage and the reference voltage to the first differential input stage when the amplifier input signal is greater than the threshold signal.

    APPARATUS AND METHOD FOR PRECHARGING A LOAD
    5.
    发明申请
    APPARATUS AND METHOD FOR PRECHARGING A LOAD 有权
    装载和预付货物的方法

    公开(公告)号：US20170040959A1

    公开(公告)日：2017-02-09

    申请号：US14818126

    申请日：2015-08-04

    Applicant: Analog Devices Global

    Inventor： Gerard Mora-Puchalt

    IPC: H03F3/217 ,  H03F1/02 ,  H03M1/12

    CPC classification number: H03F3/2175 ,  H03F1/0205 ,  H03F1/303 ,  H03F3/2171 ,  H03F3/303 ,  H03F3/45179 ,  H03F3/45219 ,  H03F3/45748 ,  H03F3/45775 ,  H03F2200/231 ,  H03F2200/297 ,  H03F2203/45112 ,  H03F2203/45116 ,  H03F2203/45292 ,  H03F2203/45454 ,  H03M1/12

    Abstract: An output stage of a buffer or an amplifier connected to a switched capacitive load can operate in two phases to perform precharging and fine settling. The precharging and fine settling phases can be synchronized to the switching phases of the switched capacitive load connected to the amplifier. During the precharging phase, the output stage can be disconnected from the prior stages of the amplifier, and the output node of the amplifier can be connected to the switched capacitive load to precharge the capacitive load with the voltage already stored in the output stage. During the fine settling phase, the output stage can be reconnected to the prior stages of the amplifier, and the amplifier nodes can settle and get ready for sampling, which can occur at the end of the fine settling phase.

    Abstract translation: 连接到开关电容性负载的缓冲器或放大器的输出级可以分两个阶段进行，以执行预充电和精细的稳定。 预充电和精细建立阶段可以与连接到放大器的开关电容负载的开关相位同步。 在预充电阶段，输出级可以与放大器的前级断开，并且放大器的输出节点可以连接到开关容性负载，以便已经存储在输出级中的电压对电容性负载进行预充电。 在精细建立阶段期间，输出级可以重新连接到放大器的前级，并且放大器节点可以稳定并准备好进行采样，这可以在微调阶段结束时发生。

    OPERATIONAL AMPLIFIER
    7.
    发明申请
    OPERATIONAL AMPLIFIER 审中-公开

    公开(公告)号：US20180198417A1

    公开(公告)日：2018-07-12

    申请号：US15401522

    申请日：2017-01-09

    Applicant: Analog Devices Global

    Inventor： Sharad Vijaykumar ,  Gerard Mora-Puchalt

    IPC: H03F1/30 ,  H03F1/26 ,  H03F3/45

    CPC classification number: H03F1/301 ,  H03F1/26 ,  H03F3/45273 ,  H03F3/45753 ,  H03F2203/45462

    Abstract: The amplifier circuit includes a pair of differential input stages coupled to an output stage where both a selected input stage and an unselected input stage are active with one of either a differential input signal or a reference voltage. A switching network couples a first input differential signal to a first differential input stage and a reference voltage to a second differential input stage when an amplifier input signal is less than a threshold voltage. The switching circuit also couples the second input differential signal to the second differential input stage and the reference voltage to the first differential input stage when the amplifier input signal is greater than the threshold signal.

    Low noise precision input stage for analog-to-digital converters
    9.
    发明授权
    Low noise precision input stage for analog-to-digital converters 有权
    模数转换器的低噪声精度输入级

    公开(公告)号：US09391628B1

    公开(公告)日：2016-07-12

    申请号：US14967880

    申请日：2015-12-14

    Applicant: ANALOG DEVICES GLOBAL

    Inventor： Colin G. Lyden ,  Pasquale Delizia ,  Sanjay Rajasekhar ,  Yogesh Jayarman Sharma ,  Arthur J. Kalb ,  Marvin L. Shu ,  Gerard Mora-Puchalt ,  Roberto S. Maurino

    IPC: H03M1/38 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12

    CPC classification number: H03M1/1245 ,  G11C27/026

    Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.

    Abstract translation: 模数转换器（ADC）的输入级包括至少一个用于采集相位中的输入信号的采样电容器（SC），用于向SC提供输入信号的电容增益放大器（CGA）以及带宽控制装置 。 带宽控制装置被配置为确保SC在获取阶段的第一部分期间具有第一带宽，并且在所述获取阶段的后续，第二部分期间具有第二带宽，第二带宽小于第一带宽。 以这种方式，首先，以更高的第一带宽对输入信号进行采样，从而可利用使用高带宽CGA来最小化SC上的稳定误差，并且接下来在相同获取阶段的第二部分期间 ，输入信号以较低，第二带宽进行采样，有利于降低使用高带宽CGA导致的噪声。

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